doi: 10.7873/DATE.2015.1111

Monolithic 3D Integration: A Path from Concept to Reality

Max M. Shulaker1,2, Tony F. Wu1,2, Mohamed M. Sabry1,2, Hai Wei1,2, H.-S. Philip Wong1,2 and Subhasish Mitra1,2,3

1Department of Electrical Engineering, Stanford University, USA

2Stanford SystemX Alliance, Stanford University, USA

3Department of Computer Science, Stanford University, USA


Monolithic three-dimensional (3D) integration enables revolutionary digital system architectures of computation immersed in memory. Vertically-stacked layers of logic circuits and memories, with nano-scale inter-layer vias (with the same pitch and dimensions as tight-pitched metal layer vias), provide massive connectivity between the layers. The nano-scale inter-layer vias are orders of magnitude denser than conventional through silicon vias (TSVs). Such digital system architectures can achieve significant performance and energy efficiency benefits compared to today’s designs. The massive vertical connectivity makes such architectures particularly attractive for abundant-data applications that impose stringent requirements with respect to low-latency data processing, high-bandwidth data transfer, and energyefficient storage of massive amounts of data. We present an overview of our progress toward realizing monolithic 3D ICs, enabled by recent advances in emerging nanotechnologies such as carbon nanotube field-effect transistors and emerging memory technologies such as Resistive RAMs and Spin-Transfer Torque RAMs.

Full Text (PDF)