Hardware Trojan Detection by Delay and Electromagnetic Measurements
X.-T. Ngo2,c, I. Exurville1,3,a,h, S. Bhasin2,d, J.-L. Danger2,4,e,j, S. Guilley2,4,f,k, Z. Najm2,g, J.-B. Rigaud3,i and B. Robisson1,b
1CEA-Tech PACA, LSAS, Gardanne, France.
2TELECOM ParisTech, Paris, France.
3EMSE, LSAS, Gardanne, France.
4Secure-IC S.A.S., Paris & Rennes, France.
Hardware Trojans (HT) inserted in integrated circuits have received special attention of researchers. In this paper, we present firstly a novel HT detection technique based on path delays measurements. A delay model, which considers intra-die process variations, is established for a net. Secondly, we show how to detect HT using ElectroMagnetic (EM) measurements. We study the HT detection probability according to its size taking into account the inter-die process variations with a set of FPGA. The results show, for instance, that there is a probability greater than 95% with a false negative rate of 5% to detect a HT larger than 1:7% of the original circuit.
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