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doi: 10.7873/DATE.2015.1076
TAPP: Temperature-Aware Application Mapping for NoC-Based Many-Core Processors
Di Zhu1,a, Lizhong Chen2, Timothy M. Pinkston1,b and Massoud Pedram1,c
1Ming Hsieh Department of Electrical Engineering, University of Southern California, Los Angeles, United States.
adizhu@usc.edu
btpink@usc.edu
cpedram@usc.edu
2School of Electrical Engineering and Computer Science, Oregon State University, Corvallis, United States.
chenliz@eecs.oregonstate.edu
ABSTRACT
Application mapping with its ability to spread out high-power components can potentially be a good approach to mitigate the looming issue of hotspots in many-core processors. However, very few works have explored effective ways of making tradeoff between temperature and network latency. Moreover, on-chip routers, which are of high power density and may lead to hotspots, are not considered in these works. In this paper, we propose TAPP (Temperature-Aware Partitioning and Placement), an efficient application mapping algorithm to reduce on-chip hotspots while sacrificing little network performance. This algo-rithm “spreads” high-power cores and routers across the chip by performing hierarchical bi-partitioning of the cores and concur-rently conducting placement of the cores onto tiles, and achieves high efficiency and superior scalability. Simulation results show that the proposed algorithm reduces the temperature by up to 6.80°C with minimal latency increase compared to the latency-oriented mapping solution.
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