In-Place Memory Mapping Approach for Optimized Parallel Hardware Interleaver Architectures
Saeed Ur Reehman, Cyrille Chavet, Philippe Coussy and Awais Sani
Lab-STICC laboratory / Université de Bretagne Sud, Lorient, France
Due to their impressive error correction performances, turbo-codes or LDPC architectures are now widely used in communication systems and are one of the most critical parts of decoders. In order to achieve high throughput requirements these decoders are based on parallel architectures, which results in a major problem to be solved: parallel memory access conflicts. To solve these conflicts, different approaches have been proposed in state of the art resulting in a lot of different architectural solutions. In this article, we introduce a new class of memory mapping approach solving the conflicts with an optimized architecture based on in-place memory mapping for any application.
Keywords: Interleaver, Memory mapping, Architecture, Error correction codes.
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