Reducing Energy Consumption in Microcontroller-Based Platforms with Low Design Margin Co-Processors
Andres Gomez1,2,a, Christian Pinto3,d, Andrea Bartolini2,3,b, Davide Rossi3,e, Luca Benini2,3,c, Hamed Fatemi4,f and Jose Pineda de Gyvez4,g
1Computer Engineering and Networks Laboratory, ETH Zurich, Switzerland
2Integrated Systems Laboratory, ETH Zurich, Switzerland.
3DEI, University of Bologna, Italy.
4NXP Semiconductors, Central R&D, The Netherlands.
Advanced energy minimization techniques (i.e. DVFS, Thermal Management, etc) and their high-level HW/SW requirements are well established in high-throughput multicore systems. These techniques would have an intolerable overhead in low-cost, performance-constrained microcontroller units (MCU’s). These devices can further reduce power by operating at a lower voltage, at the cost of increased sensitivity to PVT variation and increased design margins. In this paper, we propose an runtime environment for next-generation dualcore MCU platforms. These platforms complement a singlecore with a low area overhead, reduced design margin shadowprocessor. The runtime decreases the overall energy consumption by exploiting design corner heterogeneity between the two cores, rather than increasing the throughput. This allows the platform’s power envelope to be dynamically adjusted to application-specific requirements. Our simulations show that, depending on the ratio of core to platform energy, total energy savings can be up to 20%.
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