doi: 10.7873/DATE.2015.1008

ABSTRACT

The two-dimensional (2D) spatial median filter is the most commonly used filter for image denoising. Since it is a non-linear sorting based filter, it has high computational complexity. Therefore, in this paper, we propose a novel low complexity 2D adaptive median filter algorithm. The proposed algorithm reduces the computational complexity of 2D median filter by exploiting the pixel correlations in the input image, and it produces higher quality filtered images than 2D median filter. We also designed and implemented a low energy 2D adaptive median filter hardware implementing the proposed 2D adaptive median filter algorithm. The proposed hardware is verified to work correctly on a Xilinx Zynq 7000 FPGA board. It can process 105 full HD (1920x1080) images per second in the worst case on a Xilinx Virtex 6 FPGA, and it has more than 80% less energy consumption than original 2D median filter hardware on the same FPGA.

Keywords: Median filter, Hardware implementation, FPGA, Low energy.

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