doi: 10.7873/DATE.2015.0870


Sub-10 nm FinFETs and Tunnel-FETs: From Devices to Systems


Ankit Sharmaa, A. Arun Goudb and Kaushik Royc

School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA.

asharm142@purdue.edu
barungoud@purdue.edu
ckaushik@purdue.edu

ABSTRACT

In this paper, a detailed device/circuit/system level assessment of sub-10nm GaSb-InAs Tunneling Field Effect Transistors (TFET) versus Silicon FinFETs operating at nearthreshold voltages is reported. A source underlapped GaSb-InAs TFET is used to achieve lower subthreshold swings than previously reported TFETs and an analytical justification is provided to explain the observed improvement. Through atomistic, 2D ballistic simulations using self-consistently, coupled Non-equilibrium Green's Function (NEGF)-Poisson approach, GaSb-InAs TFET and Silicon FinFET device characteristics are derived from which compact models are extracted for SPICE simulations. Circuit simulations of a 6-stage inverter chain show that sub-10nm underlapped TFETs are especially suited for near-threshold computing because of their ability to achieve higher throughput while consuming ˜ 100x lower power compared to Si FinFETs. To analyze the suitability of sub-10 nm TFETs for medium-throughput and ultra-low power applications in future very large scale integrated designs, a LEON3 processor is synthesized at VDD = 0.25V. The impact of interconnect parasitics on the performance of TFETs is considered by studying the power-performance of the LEON3 under varying wire-load conditions. Under moderate interconnect parasitics, TFETs-based processor is shown to exhibit more than 50% power reduction compared to FinFETs.

Keywords: Double-Gate (DG), FinFET, Heterojunction TFET (Het-j TFET), International Technology Roadmap for Semiconductors (ITRS), LEON3 processor, Subthreshold Swing (SS), Tunnel Field-Effect Transistors (TFETs).


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