Interplay of Loop Unrolling and Multidimensional Memory Partitioning in HLS
Alessandro Cilardoa and Luca Gallob
Department of Electrical Engineering and Information Technologies, University of Naples Federico II
via Claudio 21, Italy.
This paper deals with memory partitioning in the
context of high-level synthesis for FPGA technologies. In particular,
the work focuses on the area overhead caused by partitioning
and sheds light on the interplay with a technique commonly used
in HLS, i.e., loop unrolling. As a practical outcome, the study
proposes a solution to reduce the area overhead by appropriately
controlling the degree of loop unrolling. The experimental results
confirm the significance of the analysis as well as the effectiveness
of the proposed optimization technique.
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