Power-Aware Online Testing of Manycore Systems in the Dark Silicon Era
Mohammad-Hashem Haghbayan1,a, Amir-Mohammad Rahmani1,b, Mohammad Fattah1,c, Pasi Liljeberg1,d, Juha Plosila1,e, Zainalabedin Navabi2 and Hannu Tenhunen1,3
1Department of Information Technology, University of Turku, Turku, Finland.
2School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Iran.
3School of ICT, KTH Royal Institute of Technology, Stockholm, Sweden.
Online defect screening techniques to detect runtime faults are becoming a necessity in current and near future technologies. At the same time, due to aggressive technology scaling into the nanometer regime, power consumption is becoming a significant burden. Most of today's chips employ advanced power management features to monitor the power consumption and apply dynamic power budgeting (i.e., capping) accordingly to prevent over-heating of the chip. Given the notable power dissipation of existing testing methods, one needs to efficiently manage the power budget to cover test process of a many-core system in runtime. In this paper, we propose a power-aware online testing method for many-core systems benefiting from advanced power management capabilities. The proposed poweraware method uses non-intrusive online test scheduling strategy to functionally test the cores in their idle period. In addition, we propose a test-aware utilization-oriented runtime mapping technique that considers the utilization of cores and their test criticality in the mapping process. Our extensive experimental results reveal that the proposed power-aware online testing approach can efficiently utilize temporarily free resources and available power budget for the testing purposes, within less than 1% penalty on system throughput for the 16nm technology.
Keywords: Online testing, Functional testing, Dark silicon, Power capping, Many-core systems.
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