A Coupling Area Reduction Technique Applying ODC Shifting
Yi Diao1,a, Tak-Kei Lam1,b, Xing Wei1,c and Yu-Liang Wu2
1Computer Science and Engineering, The Chinese University of Hong Kong, Hong Kong.
2Easy-Logic Technology Ltd., Hong Kong.
Circuit size reduction is a basic problem in today's integrated circuit (IC) design. Besides yielding a smaller area, reducing circuit size can also provide advantages in many operations throughout the design flow, including technology mapping, verification and place-and-route. In recent years, some node based logic synthesis algorithms have been proposed for this purpose. Node Addition and Removal (NAR) and Observability Don't Cares (ODCs) based node merging were found to be quite effective in reducing the number of nodes in a netlist. However, both methods do not address the effect of re-distributing ODCs and the results are virtually fixed after one iteration run. We study the implications of redistributing ODCs and propose a nodebased and wire-based coupling synthesis scheme that can effectively find better solutions with the application of ODC shifting operations. Experimental results show that this approach can produce area reductions nearly double of the pure node-based algorithms.
Keywords: Node merging, Rewiring, Area reduction, Logic synthesis.
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