doi: 10.7873/DATE.2015.0616

Automatic Extraction of Micro-Architectural Models of Communication Fabrics from Register Transfer Level Designs

Sebastiaan J. C. Joosten1,2,a and Julien Schmaltz1,b

1Eindhoven University of Technology, The Netherlands.

2Radboud University Nijmegen, The Netherlands


Multi-core processors and Systems-on-Chips are composed of a large number of processing and memory elements interconnected by complex communication fabrics. These fabrics are large systems made of many queues and distributed control logic. Recent studies have demonstrated that high levels models of these networks are either tractable for verification or can provide key invariants to improve hardware model checkers. Formally verifying Register Transfer Level (RTL) designs of these networks is an important challenge, yet still open. This paper bridges the gap between high level models and RTL designs. We propose an algorithm that from a Verilog description automatically produces its corresponding micro-architectural model. We prove that the extracted model is transfer equivalent to the original RTL circuit. We illustrate our approach on a typical example of communication fabrics: a scoreboard with credit-flow control.

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