An Energy-Efficient Virtual Channel Power-Gating Mechanism for On-Chip Networks
Amirhossein Mirhosseini1,a, Mohammad Sadrosadati1,b, Ali Fakhrzadehgan1,c, Mehdi Modarressi2,3,d and Hamid Sarbazi-Azad1,3,e,f
1Department of Computer Engineering, Sharif University of Technology, Tehran, Iran.
2School of Electrical and Computer Engineering, Faculty of Engineering, University of Tehran, Tehran, Iran
3Computer Science School, Institute for Researches in Fundamental Sciences, Tehran, Iran.
Power-gating is a promising method for reducing the leakage power of digital systems. In this paper, we propose a novel power-gating scheme for virtual channels in on-chip networks that uses an adaptive method to dynamically adjust the number of active VCs based on the on-chip traffic characteristics. Since virtual channels are used to provide higher throughput under high traffic loads, our method sets the number of virtual channel at each port selectively based on the workload demand, thereby do not negatively affect performance. Evaluation results show that by using this scheme, about 40% average reduction in static power consumption can be achieved with negligible performance overhead.
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