doi: 10.7873/DATE.2015.0463

Fast Eye Diagram Analysis for High-Speed CMOS Circuits

Seyed Nematollah Ahmadyan^1,a, Chenjie Gu^2,b, Suriyaprakash Natarajan^2,c, Eli Chiprout^2,d and Shobha Vasudevan^1,e

¹University of Illinois at Urbana-Champaign, USA

^aahmadya2@illinois.edu ^eshobhav@illinois.edu

²Intel Corporation, USA

^bchenjie.gu@intel.com ^csuriyaprakash.natarajan@intel.com ^deli.chiprout@intel.com

ABSTRACT

We present an efficient technique for analyzing eye diagrams of high speed CMOS circuits in the presence of nonidealities like noise and jitter. Our method involves geometric manipulations of the eye diagram topology to find area within the eye contours. We introduce random tree based simulations as an approach to computing the desired area. We typically show 20× speedup in generating the eye diagram as compared to the state-of-the-art Monte Carlo simulation based eye diagram analysis. For the same number of samples, Monte Carlo produces an eye diagram that is 8.51% smaller than the ideal eye diagram. We generate an eye diagram that is 53.52% smaller than the ideal eye, showing a 47% improvement in quality.

Keywords: Eye diagram analysis, Random tree optimization, Signal integrity, Nonlinear analog circuits.

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Fast Eye Diagram Analysis for High-Speed CMOS Circuits

Seyed Nematollah Ahmadyan1,a, Chenjie Gu2,b, Suriyaprakash Natarajan2,c, Eli Chiprout2,d and Shobha Vasudevan1,e

1University of Illinois at Urbana-Champaign, USA

2Intel Corporation, USA

ABSTRACT

Seyed Nematollah Ahmadyan^1,a, Chenjie Gu^2,b, Suriyaprakash Natarajan^2,c, Eli Chiprout^2,d and Shobha Vasudevan^1,e

¹University of Illinois at Urbana-Champaign, USA

²Intel Corporation, USA