MRP: Mix Real Cores and Pseudo Cores for FPGA-Based Chip-Multiprocessor Simulation
Xinke Chen1,2,a, Guangfei Zhang3, Huandong Wang4, Ruiyang Wu1,2,b, Peng Wu1,2,c and Longbing Zhang1,d
1State Key Laboratory of Computer Architecture, ICT, CAS, Beijing 100190, China.
2University of Chinese Acedemic of Science, Beijing 100094, China
3Shannon Laboratory, Huawei Technologies Co., Ltd, China
4Loongson Corporation, Beijing 100190, China.
Facing the speed bottleneck of software-based simulators, FPGA-based simulation has been explored more and more. This paper proposes a novel methodology to simulate a chip-multiprocessor (CMP) on the limited FPGA resource. By mixing real cores and pseudo cores together (MRP), we can simulate a multicore system with fewer FPGA resource requirements and achieve a much higher simulation speed. We propose several methods to construct the pseudo cores. We implement our idea on a dual Virtex-6 FPGA board to simulate a general-purpose 4-core high performance CMP processor. Comparison experiments against the corresponding tape-out chip prove the effectiveness of MRP. We also evaluate MRP prototype’s performance by running SPEC CPU2006 benchmarks on an unmodified Linux operating system, achieving tens to hundreds speedup compared to two other commonly-used simulators.
Keywords: Simulation, Emulation, CMP, Multicore, Pseudo core, FPGA.
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