Clock Domain Crossing Aware Sequential Clock Gating
Jianfeng Liu1,a, Mi-Suk Hong1,b, Kyungtae Do1,c, Jung Yun Choi1,d, Jaehong Park1,e, Mohit Kumar2,f, Manish Kumar2,g, Nikhil Tripathi2,h and Abhishek Ranjan2,i
1S. LSI, Samsung Electronics Co. Ltd., Hwasong-Si Korea.
2Calypto Design Systems Inc., Noida, India.
Power has become the overriding concern for most modern electronic applications today. To reduce clock power, which is a significant portion of the dynamic power consumed by a design, sequential clock gating is increasingly getting used over and above combinational clock gating. With the shrinking device sizes and increasingly complex designs, data is frequently transferred from one clock domain to the other. The sequential clock gating optimizations can use signals from across sequential boundaries and thus, can introduce new clock domain crossing (CDC) violations which can cause catastrophic functional issues in the fabricated chip. Hence, it has become very important that sequential clock gating optimizations be CDC aware.
In this paper, we present an algorithm to handle CDC violations as part of the objective function for sequential clock gating optimizations. With the proposed algorithm, we have obtained an average of 22% sequential power savings – this is within 3% of the power savings obtained by the CDC unaware sequential clock gating. In comparison, the state-of-the-art two-pass solution is leading to an almost complete loss of power savings.
Keywords: Clock domain crossing, Sequential clock gating, Sequential analysis, Sequential optimization, Observability, Stability, Power analysis, Power optimization.
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