Variation-Aware, Reliability-Emphasized Design and Optimization of RRAM using SPICE Model
H. Li1,2, Z. Jiang1, P. Huang2, Y. Wu1, H.-Y. Chen1, B. Gao2, X. Y. Liu2, J. F. Kang2,b and H.-S. P. Wong1,a
1Department of Electrical Engineering and Stanford SystemX Alliance, Stanford University, Stanford, CA 94305, USA.
2Institute of Microelectronics, Peking University, Beijing 100871, China.
Resistive switching random access memory (RRAM) is a leading candidate for next-generation nonvolatile and storage-class memories and monolithic integration of logic with memory interleaved in multiple layers. To meet the increasing need for device-circuit-system co-design and optimization for applications from digital memory systems to brain-inspired computing systems, a SPICE model of RRAM that can reproduce essential device physics in a circuit simulation environment is required. In this work, we develop an RRAM SPICE model that can capture all the essential device characteristics such as stochastic switching behaviors, multi-level cell, switching voltage variations, and resistance distributions. The model is verified and calibrated by a variety of electrical measurements on ~10 nm RRAMs. The model is applied to explore a wide range of applications including: 1) variationaware design; 2) reliability-emphasized design; 3) speed-power assessment; 4) array architecture optimization; and 5) neuromorphic computing. This experimentally verified design tool not only enables system design that utilizes the complete suite of RRAM device features, but also provides solutions for system optimization that capitalize on device/circuit interaction.
Keywords: Emerging memory, Resistive switching memory, SPICE model, Design tool, Variability, Reliability.
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