An Energy Efficient Backup Scheme with Low Inrush Current for Nonvolatile SRAM in Energy Harvesting Sensor Nodes
Hehe Li1,a, Yongpan Liu1,b, Qinghang Zhao1,c, Yizi Gu1,d, Xiao Sheng1,e, Guangyu Sun2,h, Chao Zhang2,i, Meng-Fan Chang3, Rong Luo1,f and Huazhong Yang1,g
1Tsinghua National Laboratory for Information Science and Technology, Department of Electronic Engineering, Tsinghua University, Haidian 100084, Beijing, China.
2Center for Energy-efficient Computing and Applications, EECS School, Peking University, Haidian 100871, Beijing, China.
3Department of Electrical Engineering, National Tsing Hua University, Hsin Chu 30013, Taiwan.
In modern energy harvesting sensor nodes, non-
volatile SRAM (nvSRAM) has been widely investigated as a
promising on-chip memory architecture because of its zero
standby power, resilience to power failures, and fast read/write
operations. However, conventional approaches transfer all data
from SRAM into NVM during the backup process. Thus, large
on-chip energy storage capacitors are normally required. In
addition, high peak inrush current is generated instantaneously,
which has a negative impact on energy efficiency and circuit
To mitigate these problems, we propose a novel holistic backup
flow, which consists of a partial backup process and a run-time
pre-writeback scheme for nvSRAM based caches. A statistics
based dead-block predictor is employed to achieve a fast and
low power partial backup process. We also present an adaptive
pre-writeback point allocation strategy to further reduce the
backup load. Simulation results show that, with our proposed
backup scheme, energy storage capacitance is reduced by 34%
and inrush current is reduced by 54% on average compared to
the conventional full backup scheme.
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