GPU-Accelerated Small Delay Fault Simulation
Eric Schneider1,a, Stefan Holst2,d, Michael A. Kochte1,b,
Xiaoqing Wen2,e and Hans-Joachim Wunderlich1,c
1University of Stuttgart, Pfaffenwaldring, Stuttgart, Germany.
2Kyushu Institute of Technology, Kawazu, Iizuka, Japan.
The simulation of delay faults is an essential task in design validation and reliability assessment of circuits. Due to the high sensitivity of current nano-scale designs against smallest delay deviations, small delay faults recently became the focus of test research. Because of the subtle delay impact, traditional fault simulation approaches based on abstract timing models are not sufficient for representing small delay faults. Hence, timing accurate simulation approaches have to be utilized, which quickly become inapplicable for larger designs due to high computational requirements. In this work we present a waveform-accurate approach for fast high-throughput small delay fault simulation on Graphics Processing Units (GPUs). By exploiting parallelism from gates, faults and patterns, the proposed approach enables accurate exhaustive small delay fault simulation even for multi-million gate designs without fault dropping for the first time.
Full Text (PDF)