A CNN-Inspired Mixed Signal Processor Based on
Behnam Sedighia, Indranil Palitb, X. Sharon Huc, Joseph Nahasd and Michael Niemiere
Department of Computer Science and Engineering, University of Notre Dame, Notre Dame, IN, USA.
Novel devices are under investigation to extend the performance scaling trends that have long been associated with Moore‘s Law-based device scaling. Among the emerging devices being studied, tunnel FETs (or TFETs) are particularly attractive, especially when targeting low power systems. This paper studies the potential of analog/mixed-signal information processing using TFETs. The design of a highly-parallel processor – inspired by cellular neural networks – is presented. Signal processing is performed partially in the time-domain to better leverage the unique properties of TFETs, i.e., (i) steep slopes (high gm/IDS) in the subthreshold region, and (ii) high output resistance in the saturation region. Assuming an InAs TFET with feature sizes comparable to the 14 nm technology node, a power efficiency of 10,000 GOPS/W is projected. By comparison, state-of-theart hardware assuming CMOS technology promises a power efficiency only close to 1,000 GOPS/W.
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