doi: 10.7873/DATE.2015.0025

Efficient Bit Error Rate Estimation for High-Speed Link by Bayesian Model Fusion

Chenlei Fang¹, Qicheng Huang¹, Fan Yang^1,a, Xuan Zeng^1,b, Xin Li^1,2 and Chenjie Gu³

¹State Key Lab of ASIC & System, Microelectronics Department, Fudan University, Shanghai, P. R. China.

^ayangfan@fudan.edu.cn ^bxzeng@fudan.edu.cn

²Electrical & Computer Engineering Department, Carnegie Mellon University, Pittsburgh, PA, USA

³Intel Strategic CAD Labs, USA

ABSTRACT

High-speed I/O link is an important component in computer systems, and estimating its bit error rate (BER) is a critical task to guarantee its performance. In this paper, we propose an efficient method to estimate BER by Bayesian Model Fusion. Its key idea is to borrow conventional extrapolated BER value as prior knowledge, and combine it with additional measurement data to “calibrate” the BER value. This method can be viewed as an application of Bayesian Model Fusion (BMF) technique. We further propose some novel methodologies to make BMF applicable in the BER estimation case. In this way, we can sufficiently decrease the number of bits needed to estimate BER value. Several experiments demonstrate that our proposed method achieves up to 8x speed-up over direct estimation method.

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Efficient Bit Error Rate Estimation for High-Speed Link by Bayesian Model Fusion

Chenlei Fang1, Qicheng Huang1, Fan Yang1,a, Xuan Zeng1,b, Xin Li1,2 and Chenjie Gu3

1State Key Lab of ASIC & System, Microelectronics Department, Fudan University, Shanghai, P. R. China.

2Electrical & Computer Engineering Department, Carnegie Mellon University, Pittsburgh, PA, USA

3Intel Strategic CAD Labs, USA

ABSTRACT

Chenlei Fang¹, Qicheng Huang¹, Fan Yang^1,a, Xuan Zeng^1,b, Xin Li^1,2 and Chenjie Gu³

¹State Key Lab of ASIC & System, Microelectronics Department, Fudan University, Shanghai, P. R. China.

²Electrical & Computer Engineering Department, Carnegie Mellon University, Pittsburgh, PA, USA

³Intel Strategic CAD Labs, USA