Date: Thursday 12 March 2020
Time: 08:30 - 10:00
Location / Room: Berlioz

Chair:
Pavlidis Vasilis, The University of Manchester, GB

Co-Chair:
Bing Li, TU Munich, DE

This session examines a diverse set of applications for emerging technologies. Papers consider the use of Q-learning to perform more efficient backups in non-volatile processors, the use of emerging technologies to mitigate hardware side-channels, time-sequence-based classification that rise from ultrasonic patters due to hand movements for gesture recognition, and processing-in-memory-based solutions to accelerate DNA alignment searches.

Time	Label	Presentation Title Authors
08:30	9.7.1	Q-LEARNING BASED BACKUP FOR ENERGY HARVESTING POWERED EMBEDDED SYSTEMS Speaker: Wei Fan, Shandong University, CN Authors: Wei Fan, Yujie Zhang, Weining Song, Mengying Zhao, Zhaoyan Shen and Zhiping Jia, Shandong University, CN Abstract Non-volatile processors (NVPs) are used in energy harvesting powered embedded systems to preserve data across interruptions. In NVP systems, volatile data are backed up to non-volatile memory upon power failures and resumed after power comes back. Traditionally, backup is triggered immediately when energy warning occurs. However, it is also possible to more aggressively utilize the residual energy for program execution to improve forward progress. In this work, we propose a Q-learning based backup strategy to achieve maximal forward progress in energy harvesting powered intermittent embedded systems. The experimental results show an average of 307.4% and 43.4% improved forward progress compared with traditional instant backup and the most related work, respectively. Download Paper (PDF; Only available from the DATE venue WiFi)
09:00	9.7.2	A NOVEL TIGFET-BASED DFF DESIGN FOR IMPROVED RESILIENCE TO POWER SIDE-CHANNEL ATTACKS Speaker: Michael Niemier, University of Notre Dame, US Authors: Mohammad Mehdi Sharifi1, Ramin Rajaei1, Patsy Cadareanu2, Pierre-Emmanuel Gaillardon2, Yier Jin3, Michael Niemier1 and X. Sharon Hu1 1University of Notre Dame, US; 2University of Utah, US; 3University of Florida, US Abstract Side-channel attacks (SCAs) represent a significant security threat, and aim to reveal otherwise secret data by analyzing a relevant circuit's behavior, e.g., its power consumption. While all circuit components are potential power side channels, D-flip-flops (DFFs) are often the primary source of information leakage to an SCA. This paper proposes a DFF design based on the three-independent-gate field-effect transistor (TIGFET) that reduces side-channel vulnerabilities of sequential circuits. Notably, we find that the I-V characteristics of the TIGFET itself leads to inherent side-channel resilience, which in turn enables simpler and more efficient cryptographic hardware. Our proposed design is based on a prior TIGFET-based true single-phase clock (TSPC) DFF design, which offers high performance and reduced area. More specifically, our modified TSPC (mTSPC) design exploits the symmetric I-V characteristics of TIGFETs, which results in pull-up and pull-down currents that are nearly identical. When combined with additional circuit modifications (made possible by the unique characteristics of the TIGFET), the mTSPC circuit draws almost the same amount of supply currents under all possible input transitions (less than 1% variation for different transitions), which can in turn mask information leakage. Using a 10nm TIGFET technology model, simulation results show that the proposed TIGFET-based DFF circuit leads to decreased power consumption (up to 96.9% when compared to the prior secured designs), has a low delay (15.2 ps), and employs only 12 TIGFET devices. Furthermore, an 8-bit S-box whose output is sampled by a group of eight mTSPC DFFs was simulated. A correlation power analysis attack on the simulated S-box with 256 power traces shows that the key is not revealed, which confirms the SCA resiliency of the proposed DFF design. Download Paper (PDF; Only available from the DATE venue WiFi)
09:30	9.7.3	LOW COMPLEXITY MULTI-DIRECTIONAL IN-AIR ULTRASONIC GESTURE RECOGNITION USING A TCN Speaker: Emad A. Ibrahim, Eindhoven University of Technology, NL Authors: Emad A. Ibrahim1, Marc Geilen1, Jos Huisken1, Min Li2 and Jose Pineda de Gyvez2 1Eindhoven University of Technology, NL; 2NXP Semiconductors, NL Abstract On the trend of ultrasound-based gesture recognition, this study introduces the concept of time-sequence classification of ultrasonic patterns induced by hand movements on a microphone array. We refer to time-sequence ultrasound echoes as continuous frequency patterns being received in real-time at different steering angles. The ultrasound source is a single tone continuously being emitted from the center of the microphone array. In the interim, the array beamforms and locates an ultrasonic activity (induced echoes) after which a processing pipeline is initiated to extract band-limited frequency features. These beamformed features are organized in a 2D matrix of size 11*30 updated every 10ms on which a Temporal Convolutional Network (TCN) outputs continuous classification. Prior to that, the same TCN is trained to classify Doppler shift variability rate. Using this approach, we show that a user can easily achieve 49 gestures at different steering angles by means of sequence detection. To make it simple to users, we define two Doppler shift variability rates; very slow and very fast which the TCN detects 95-99 % of the time. Not only a gesture can be performed at different directions but also the length of each performed gesture can be measured. This leverages the diversity of in-air ultrasonic gestures allowing more control capabilities. The process is designed under low-resource settings; that is, given the fact that this real-time process is always-on, the power and memory resources should be optimized. The proposed solution needs 6.2-10.2 MMACs and a memory footprint of 6KB allowing such gesture recognition system to be hosted by energy-constrained edge devices such as smart-speakers. Download Paper (PDF; Only available from the DATE venue WiFi)
09:45	9.7.4	PIM-ALIGNER: A PROCESSING-IN-MRAM PLATFORM FOR BIOLOGICAL SEQUENCE ALIGNMENT Speaker: Deliang Fan, Arizona State University, US Authors: Shaahin Angizi1, Jiao Sun1, Wei Zhang1 and Deliang Fan2 1University of Central Florida, US; 2Arizona State University, US Abstract In this paper, we propose a high-throughput and energy-efficient Processing-in-Memory accelerator (PIM-Aligner) to execute DNA short read alignment based on an optimized and hardware-friendly alignment algorithm. We first reconstruct the existing sequence alignment algorithm based on BWT and FM-index such that it can be fully implemented in PIM platforms. It supports exact alignment and also handles mismatches to reduce excessive backtracking. We then develop PIM-Aligner platform that transforms SOT-MRAM array to a potential computational memory to accelerate the reconstructed alignment-in-memory algorithm incurring a low cost on top of original SOT-MRAM chips (less than 10% of chip area). Accordingly, we present a local data partitioning, mapping, and pipeline technique to maximize the parallelism in multiple computational sub-array while doing the alignment task. The simulation results show that PIM-Aligner outperforms recent platforms based on dynamic programming with ~3.1x higher throughput per Watt. Besides, PIM-Aligner improves the short read alignment throughput per Watt per mm^2 by ~9x and 1.9x compared to FM-index-based ASIC and processing-in-ReRAM designs, respectively. Download Paper (PDF; Only available from the DATE venue WiFi)
10:00	IP4-17, 852	TRANSPORT-FREE MODULE BINDING FOR SAMPLE PREPARATION USING MICROFLUIDIC FULLY PROGRAMMABLE VALVE ARRAYS Speaker: Gautam Choudhary, Adobe Research, India, IN Authors: Gautam Choudhary1, Sandeep Pal1, Debraj Kundu1, Sukanta Bhattacharjee2, Shigeru Yamashita3, Bing Li4, Ulf Schlichtmann4 and Sudip Roy1 1IIT Roorkee, IN; 2Indian Statistical Institute, IN; 3Ritsumeikan University, JP; 4TU Munich, DE Abstract Microfluidic fully programmable valve array (FPVA) biochips have emerged as general-purpose flow-based microfluidic lab-on-chips (LoCs). An FPVA supports highly re-configurable on-chip components (modules) in the two-dimensional grid-like structure controlled by some software programs, unlike application-specific flow-based LoCs. Fluids can be loaded into or washed from a cell with the help of flows from the inlet to outlet of an FPVA, whereas cell-to-cell transportation of discrete fluid segment(s) is not precisely possible. The simplest mixing module to realize on an FPVA-based LoC is a four-way mixer consisting of a $2imes2$ array of cells working as a ring-like mixer having four valves. In this paper, we propose a design automation method for sample preparation that finds suitable placements of mixing operations of a mixing tree using four-way mixers without requiring any transportation of fluid(s) between modules. We also propose a heuristic that modifies the mixing tree to reduce the sample preparation time. We have performed an extensive simulation and examined several parameters to determine the performance of the proposed solution. Download Paper (PDF; Only available from the DATE venue WiFi)
10:00		End of session