9.1 Special Day on "Silicon Photonics": Advancements on Silicon Photonics

Time	Label	Presentation Title Authors
08:30	9.1.1	SYSTEM STUDY OF SILICON PHOTOHOTONICNICS MODULATOR IN SHORT REACH GRIDLESS COHERENT NETWORKS Speaker: Sadok Aouini, Ciena Corporation, CA Authors: Sadok Aouini¹, Ahmad Abdo¹, Xueyang Li², Md Samiul Alam², Mahdi Parvizi¹, Claude D'Amours³ and David V. Plant² ¹Ciena Corporation, CA; ²McGill University, CA; ³University of Ottawa, CA Abstract A study the impact of modulation loss of Silicon-Photonics Mach-Zehnder modulators in the context of single-carrier coherent receivers, i.e. 400G-ZR. The modulation loss is primarily due to limited bandwidth and large peak to overage ratio of the modulator output. We present the implications of performing only post-compensation of the loss at the receiver and its advantages in gridless-networks. A manageable Q factor penalty of around 0.5 dB is found for dual- polarization system with a 0.75 dB peak to average ratio (PAPR) reduction. Download Paper (PDF; Only available from the DATE venue WiFi)
09:00	9.1.2	FULLY INTEGRATED PHOTONIC CIRCUITS ON SILICON BY MEANS OF III-V/SILICON BONDING Author: Florian Denis-le Coarer, SCINTIL Photonics, US Abstract This presentation introduces a new platform integrating heterogeneous III-V/silicon gain devices at the backside of silicon-on-insulator wafers. The fabrication relies on commercial silicon photonic processes. This platform enables fully photonic integrated circuits comprising lasers, modulators, passives and photodetectors, that can be tested at the wafer level.
09:30	9.1.3	III-V/SILICON HYBRID LASERS INTEGRATION ON CMOS-COMPATIBLE 200MM AND 300MM PLATFORMS Speaker: Karim Hassan, CEA-Leti, FR Authors: Karim Hassan¹, Szelag Bertrand¹, Laetitia Adelmini¹, Cecilia Dupre¹, Elodie Ghegin², Philippe Rodriguez¹, Fabrice Nemouchi¹, Pierre Brianceau¹, Antoine Schembri¹, David Carrara³, Pierrick Cavalie³, Florent Franchin³, Marie-Christine Roure¹, Loic Sanchez¹, Christophe Jany¹ and Ségolène Olivier¹ ¹CEA-Leti, FR; ²STMicroelectronics, FR; ³Almae Technologies, FR Abstract We present a CMOS-compatible hybrid III-V/Silicon technology developed in CEA-Leti. Large-scale integration of silicon photonics is already available worldwide in 200mm or 300mm through different foundries, but the development of CMOS-compatible process for the III-V integration remains of major interest for next gen transceivers in the Datacom and High Performance Computing domains. The technological developments involve first the hybridization on top of a mature silicon photonic front-end wafer through direct molecular bonding, then the patterning of the III-V epitaxy layer, and low access resistance contacts though planar multilevel BEOL to be optimized. The different technological blocks will be described, and the results will be discussed on the basis of test vehicles based on either distributed feedback (DFB), distributed Bragg reflector (DBR), or Fabry-Perot (FP) laser cavities. While first demonstrations have been obtained through wafer bonding, we show that the fabrication process was subsequently validated on III-V dies bonding with a fabrication yield of Fabry-Perot lasers of 97% in 200mm. The overall technological features are expected improve the efficiency, density, and cost of silicon photonics PICs.
10:00		End of session

Time

Label

Presentation Title
Authors

08:30

9.1.1

SYSTEM STUDY OF SILICON PHOTOHOTONICNICS MODULATOR IN SHORT REACH GRIDLESS COHERENT NETWORKS
Speaker:
Sadok Aouini, Ciena Corporation, CA
Authors:
Sadok Aouini¹, Ahmad Abdo¹, Xueyang Li², Md Samiul Alam², Mahdi Parvizi¹, Claude D'Amours³ and David V. Plant²
¹Ciena Corporation, CA; ²McGill University, CA; ³University of Ottawa, CA
Abstract
A study the impact of modulation loss of Silicon-Photonics Mach-Zehnder modulators in the context of single-carrier coherent receivers, i.e. 400G-ZR. The modulation loss is primarily due to limited bandwidth and large peak to overage ratio of the modulator output. We present the implications of performing only post-compensation of the loss at the receiver and its advantages in gridless-networks. A manageable Q factor penalty of around 0.5 dB is found for dual- polarization system with a 0.75 dB peak to average ratio (PAPR) reduction.
Download Paper (PDF; Only available from the DATE venue WiFi)

09:00

9.1.2

FULLY INTEGRATED PHOTONIC CIRCUITS ON SILICON BY MEANS OF III-V/SILICON BONDING
Author:
Florian Denis-le Coarer, SCINTIL Photonics, US
Abstract
This presentation introduces a new platform integrating heterogeneous III-V/silicon gain devices at the backside of silicon-on-insulator wafers. The fabrication relies on commercial silicon photonic processes. This platform enables fully photonic integrated circuits comprising lasers, modulators, passives and photodetectors, that can be tested at the wafer level.

09:30

9.1.3

III-V/SILICON HYBRID LASERS INTEGRATION ON CMOS-COMPATIBLE 200MM AND 300MM PLATFORMS
Speaker:
Karim Hassan, CEA-Leti, FR
Authors:
Karim Hassan¹, Szelag Bertrand¹, Laetitia Adelmini¹, Cecilia Dupre¹, Elodie Ghegin², Philippe Rodriguez¹, Fabrice Nemouchi¹, Pierre Brianceau¹, Antoine Schembri¹, David Carrara³, Pierrick Cavalie³, Florent Franchin³, Marie-Christine Roure¹, Loic Sanchez¹, Christophe Jany¹ and Ségolène Olivier¹
¹CEA-Leti, FR; ²STMicroelectronics, FR; ³Almae Technologies, FR
Abstract
We present a CMOS-compatible hybrid III-V/Silicon technology developed in CEA-Leti. Large-scale integration of silicon photonics is already available worldwide in 200mm or 300mm through different foundries, but the development of CMOS-compatible process for the III-V integration remains of major interest for next gen transceivers in the Datacom and High Performance Computing domains. The technological developments involve first the hybridization on top of a mature silicon photonic front-end wafer through direct molecular bonding, then the patterning of the III-V epitaxy layer, and low access resistance contacts though planar multilevel BEOL to be optimized. The different technological blocks will be described, and the results will be discussed on the basis of test vehicles based on either distributed feedback (DFB), distributed Bragg reflector (DBR), or Fabry-Perot (FP) laser cavities. While first demonstrations have been obtained through wafer bonding, we show that the fabrication process was subsequently validated on III-V dies bonding with a fabrication yield of Fabry-Perot lasers of 97% in 200mm. The overall technological features are expected improve the efficiency, density, and cost of silicon photonics PICs.

10:00

End of session