Date: Wednesday 11 March 2020
Time: 17:00 - 18:30
Location / Room: Berlioz

Chair:
Vasilis Pavlidis, The University of Manchester, GB

Co-Chair:
L. Miguel Silveira, INESC ID / IST, U Lisboa, PT

This session deals with problems in extraction, DRC hotspots, IR drop, routing and other relevant issues in physical design and analysis. The common trend between all papers is efficiency improvement while maintaining accuracy. Floating random walk extraction is performed to handle non-stratified dielectrics with on-the-fly computations. Also, serial equivalence can be guaranteed in FPGA routing by exploring parallelism. A legalization flow is proposed for double-patterning aware feature alignment. Finally, machine-learning based DRC hotspot prediction is enhanced with explainability.

Time	Label	Presentation Title Authors
17:00	8.7.1	FLOATING RANDOM WALK BASED CAPACITANCE SOLVER FOR VLSI STRUCTURES WITH NON-STRATIFIED DIELECTRICS Speaker: Ming Yang, Tsinghua University, CN Authors: Mingye Song, Ming Yang and Wenjian Yu, Tsinghua University, CN Abstract In this paper, two techniques are proposed to enhance the floating random walk (FRW) based capacitance solver for handling non-stratified dielectrics in very large-scale integrated (VLSI) circuits. They follow an existing approach which employs approximate eight-octant transition cubes while simulating the structure with conformal dielectrics. Firstly, the symmetry property of the transition probabilities of the eightoctant cube is revealed and utilized to derive an on-the-fly sampling scheme during the FRWprocedure. This avoids the precharacterization, saves substantial memory, and improves computational accuracy for extracting the structure with non-stratified dielectrics. Then, the space management technique is extended to improve the runtime efficiency for simulating structures with thousands of non-stratified dielectrics. Numerical experiments are carried out to validate the proposed techniques and show their effectiveness for handling structures with conformal dielectrics and air bubbles. Moreover, the extended space management brings up to 1441X speedup for handling structures with from several thousand to one million non-stratified dielectrics. Download Paper (PDF; Only available from the DATE venue WiFi)
17:30	8.7.2	TOWARDS SERIAL-EQUIVALENT MULTI-CORE PARALLEL ROUTING FOR FPGAS Speaker: Minghua Shen, Sun Yat-sen University, CN Authors: Minghua Shen and Nong Xiao, Sun Yat-sen University, CN Abstract In this paper, we present a serial-equivalent parallel router for FPGAs on modern multi-core processors. We are based on the inherent net order of serial router to schedule all the nets into a series of stages, where the non-conflicting nets are scheduled in same stage and the conflicting nets are scheduled in different stages. We explore the parallel routing of non-conflicting nets on multi-core processors for a significant speedup. We perform the data synchronization of conflicting stages using MPI-based message queue for a feasible routing solution. Note that load balance is always used to guide the multi-core parallel routing. Experimental results show that our parallel router provides about 19.13x speedup on average using 32 processor cores comparing to the serial router. Notably, our parallel router generates exactly the same wirelength as the serial router satisfying serial equivalency. Download Paper (PDF; Only available from the DATE venue WiFi)
18:00	8.7.3	SELF-ALIGNED DOUBLE-PATTERNING AWARE LEGALIZATION Speaker: Hua Xiang, IBM Research, US Authors: Hua Xiang1, Gi-Joon Nam1, Gustavo Tellez2, Shyam Ramji2 and Xiaoqing Xu3 1IBM Research, US; 2IBM Thomas J. Watson Research Center, US; 3University of Texas at Austin, US Abstract Double patterning is a widely used technique for sub-22nm. Among various double patterning techniques, Self-Aligned Double Patterning (SADP) is a promising technique for good mask overlay control. Based on SADP, a new set of standard cells (T-cells) are developed using thicker metal wires for stronger drive strength. By applying this kind of gates on critical paths, it helps to improve the design performance. However, a mixed design with T-cells and normal cells (N-cells) requires that T-cells are placed on circuit rows with thicker metal, and the normal cells are on the normal circuit rows. Therefore, a placer is needed to adjust the cells to the matched circuit rows. In this paper, a two-stage min-cost max-flow based legalization flow is presented to adjust N/T gate locations for a legal placement. The experimental results demonstrate the effectiveness and efficiency of our approach. Download Paper (PDF; Only available from the DATE venue WiFi)
18:15	8.7.4	EXPLAINABLE DRC HOTSPOT PREDICTION WITH RANDOM FOREST AND SHAP TREE EXPLAINER Speaker: Wei Zeng, University of Wisconsin-Madison, US Authors: Wei Zeng1, Azadeh Davoodi1 and Rasit Onur Topaloglu2 1University of Wisconsin - Madison, US; 2IBM, US Abstract With advanced technology nodes, resolving design rule check (DRC) violations has become a cumbersome task, which makes it desirable to make predictions at earlier stages of the design flow. In this paper, we show that the Random Forest (RF) model is quite effective for the DRC hotspot prediction at the global routing stage, and in fact significantly outperforms recent prior works, with only a fraction of the runtime to develop the model. We also propose, for the first time, to adopt a recent explanatory metric--the SHAP value--to make accurate and consistent explanations for individual DRC hotspot predictions from RF. Experiments show that RF is 21%-60% better in predictive performance on average, compared with promising machine learning models used in similar works (e.g. SVM and neural networks) while exhibiting good explainability, which makes it ideal for DRC hotspot prediction. Download Paper (PDF; Only available from the DATE venue WiFi)
18:31	IP4-10, 522	XGBIR: AN XGBOOST-BASED IR DROP PREDICTOR FOR POWER DELIVERY NETWORK Speaker: An-Yu Su, National Chiao Tung University, TW Authors: Chi-Hsien Pao, Yu-Min Lee and An-Yu Su, National Chiao Tung University, TW Abstract This work utilizes the XGBoost to build a machine-learning-based IR drop predictor, XGBIR, for the power grid. To capture the behavior of power grid, we extract its several features and employ its locality property to save the extraction time. XGBIR can be effectively applied to large designs and the average error of predicted IR drops is less than 6 mV. Download Paper (PDF; Only available from the DATE venue WiFi)
18:32	IP4-11, 347	ON PRE-ASSIGNMENT ROUTE PROTOTYPING FOR IRREGULAR BUMPS ON BGA PACKAGES Speaker: Hung-Ming Chen, National Chiao Tung University, TW Authors: Jyun-Ru Jiang1, Yun-Chih Kuo2, Simon Chen3 and Hung-Ming Chen1 1National Chiao Tung University, TW; 2National Taiwan University, TW; 3MediaTek.inc, TW Abstract In modern package design, the bumps often place irregularly due to the macros varied in sizes and positions. This will make pre-assignment routing more difficult, even with massive design efforts. This work presents a 2-stage routing method which can be applied to an arbitrary bump placement on 2-layer BGA packages. Our approach combines escape routing with via assignment: the escape routing is used to handle the irregular bumps and the via assignment is applied for improving the wire congestion and total wirelength of global routing. Experimental results based on industrial cases show that our methodology can solve the routing efficiently, and we have achieved 82% improvement on wire congestion with 5% wirelength increase compared with conventional regular treatments. Download Paper (PDF; Only available from the DATE venue WiFi)
18:30		End of session