Date: Wednesday 11 March 2020
Time: 08:30 - 10:00
Location / Room: Lesdiguières

Chair:
Valeria Bertacco, University of Michigan, US

Co-Chair:
Lukas Sekanina, Brno University of Technology, CZ

The logic synthesis family is growing. While traditional optimization goals such as area and delay are still very important in todays design automation, new applications require improvement of aspects such as security or power consumption. This session showcases various algorithms addressing both emerging and traditional optimization goals. An algorithm is proposed for cryptographic applications which reduces the multiplicative complexity thereby making designs less vulnerable to attacks. A synthesis method converts flip-flops to latches in a clever way and saves power in this way. Approximation and bi-decomposition techniques are used in an area optimization strategy. Finally, a methodology for design minimization in advanced technology nodes is presented that takes both wire congestion and coupling effects into account.

Time	Label	Presentation Title Authors
08:30	5.6.1	A LOGIC SYNTHESIS TOOLBOX FOR REDUCING THE MULTIPLICATIVE COMPLEXITY IN LOGIC NETWORKS Speaker: Eleonora Testa, EPFL, CH Authors: Eleonora Testa1, Mathias Soeken1, Heinz Riener1, Luca Amaru2 and Giovanni De Micheli1 1EPFL, CH; 2Synopsys, US Abstract Logic synthesis is a fundamental step in the realization of modern integrated circuits. It has traditionally been employed for the optimization of CMOS-based designs, as well as for emerging technologies and quantum computing. Recently, it found application in minimizing the number of AND gates in cryptography benchmarks represented as xor-and graphs (XAGs). The number of AND gates in an XAG, which is called the logic network's multiplicative complexity, plays a critical role in various cryptography and security protocols such as fully homomorphic encryption (FHE) and secure multi-party computation (MPC). Further, the number of AND gates is also important to assess the degree of vulnerability of a Boolean function, and influences the cost of techniques to protect against side-channel attacks. However, so far a complete logic synthesis flow for reducing the multiplicative complexity in logic networks did not exist or relied heavily on manual manipulations. In this paper, we present a logic synthesis toolbox for cryptography and security applications. The proposed tool consists of powerful transformations, namely resubstitution, refactoring, and rewriting, specifically designed to minimize the multiplicative complexity of an XAG. Our flow is fully automatic and achieves significant results over both EPFL benchmarks and cryptography circuits. We improve the best-known results for cryptography up to 59%, resulting in a normalized geometric mean of 0.82. Download Paper (PDF; Only available from the DATE venue WiFi)
09:00	5.6.2	SAVING POWER BY CONVERTING FLIP-FLOP TO 3-PHASE LATCH-BASED DESIGNS Speaker: Peter Beerel, University of Southern California, US Authors: Huimei Cheng, Xi Li, Yichen Gu and Peter Beerel, University of Southern California, US Abstract Latches are smaller and lower power than flip-flops (FFs) and are typically used in a time-borrowing master-slave configuration. This paper presents an automatic flow for converting arbitrarily-complex single-clock-domain FF-based RTL designs to efficient 3-phase latch-based designs with reduced number of required latches, saving both register and clock-tree power. Post place-and-route results demonstrate that our 3-phase latch-based designs save an average of 15.5% and 18.5% power on a variety of ISCAS, CEP, and CPU benchmark circuits, compared to their more traditional FF and master-slave based alternatives. Download Paper (PDF; Only available from the DATE venue WiFi)
09:30	5.6.3	COMPUTING THE FULL QUOTIENT IN BI-DECOMPOSITION BY APPROXIMATION Speaker: Valentina Ciriani, University of Milan, IT Authors: Anna Bernasconi1, Valentina Ciriani2, Jordi Cortadella3 and Tiziano Villa4 1Università di Pisa, IT; 2Universita' degli Studi di Milano, IT; 3UPC, ES; 4Università di Verona, IT Abstract Bi-decomposition is a design technique widely used to realize logic functions by the composition of simpler components. It can be seen as a form of Boolean division, where a given function is split into a divisor and quotient (and a remainder, if needed). The key questions are how to find a good divisor and then how to compute the quotient. In this paper we choose as divisor an approximation of the given function, and characterize the incompletely specified function which describes the full flexibility for the quotient. We report at the end preliminary experiments for bi-decomposition based on two AND-like operators with a divisor approximation from 1 to 0, and discuss the impact of the approximation error rate on the final area of the components in the case of synthesis by three-level XOR-AND-OR forms. Download Paper (PDF; Only available from the DATE venue WiFi)
09:45	5.6.4	MINIDELAY: MULTI-STRATEGY TIMING-AWARE LAYER ASSIGNMENT FOR ADVANCED TECHNOLOGY NODES Speaker: Xinghai Zhang, Fuzhou University, CN Authors: Xinghai Zhang1, Zhen Zhuang1, Genggeng Liu1, Xing Huang2, Wen-Hao Liu3, Wenzhong Guo1 and Ting-Chi Wang2 1Fuzhou University, CN; 2National Tsing Hua University, TW; 3Cadence Design Systems, US Abstract Layer assignment, a major step in global routing of integrated circuits, is usually performed to assign segments of nets to multiple layers. Besides the traditional optimization goals such as overflow and via count, interconnect delay plays an important role in determining chip performance and has been attracting much attention in recent years. Accordingly, in this paper, we propose MiniDelay, a timing-aware layer assignment algorithm to minimize delay for advanced technology nodes, taking both wire congestion and coupling effect into account. MiniDelay consists of the following three key techniques: 1) a non-default-rule routing technique is adopted to reduce the delay of timing critical nets, 2) an effective congestion assessment method is proposed to optimize delay of nets and via count simultaneously, and 3) a net scalpel technique is proposed to further reduce the maximum delay of nets, so that the chip performance can be improved in a global manner. Experimental results on multiple benchmarks confirm that the proposed algorithm leads to lower delay and few vias, while achieving the best solution quality among the existing algorithms with the shortest runtime. Download Paper (PDF; Only available from the DATE venue WiFi)
10:00	IP2-16, 932	A SCALABLE MIXED SYNTHESIS FRAMEWORK FOR HETEROGENEOUS NETWORKS Speaker: Max Austin, University of Utah, US Authors: Max Austin1, Scott Temple1, Walter Lau Neto1, Luca Amaru2, Xifan Tang1 and Pierre-Emmanuel Gaillardon1 1University of Utah, US; 2Synopsys, US Abstract We present a new logic synthesis framework which produces efficient post-technology mapped results on heterogeneous networks containing a mix of different types of logic. This framework accomplishes this by breaking down the circuit into sections using a hypergraph k-way partitioner and then determines the best-fit logic representation for each partition between two Boolean networks, And-Inverter Graphs(AIG) and Majority-Inverter Graphs(MIG), which have been shown to perform better over each other on different types of logic. Experimental results show that over a set of Open Piton DesignBenchmarks(OPDB) and OpenCores benchmarks, our proposed methodology outperforms state-of-the-art academic tools inArea-Delay Product(ADP), Power-Delay Product(PDP), and Energy-Delay Product(EDP) by 5%, 2%, and 15% respectively after performing Application Specific Integrated Circuits(ASIC) technology mapping as well as showing a 54% improvement in runtime over conventional MIG optimization Download Paper (PDF; Only available from the DATE venue WiFi)
10:01	IP2-17, 456	DISCERN: DISTILLING STANDARD CELLS FOR EMERGING RECONFIGURABLE NANOTECHNOLOGIES Speaker: Shubham Rai, TU Dresden, DE Authors: Shubham Rai1, Michael Raitza2, Siva Satyendra Sahoo1 and Akash Kumar1 1TU Dresden, DE; 2TU Dresden and CfAED, DE Abstract Logic gates and circuits based on reconfigurable nanotechnologies demonstrate runtime-reconfigurability, where a single logic gate can exhibit more than one functionality. Recent attempts on circuits based on emerging reconfigurable nanotechnologies have primarily focused on using the traditional CMOS design flow involving similar-styled standard-cells. These CMOS-centric standard-cells fail to utilize the exciting properties offered by these nanotechnologies. In the present work, we explore the boolean properties that define the reconfigurable properties of a logic gate. By analyzing the truth-table in detail, we find that there is a common boolean rule which dictates why a logic gate is reconfigurable. Such logic gates can be efficiently implemented using reconfigurable nanotechnologies. We propose an algorithm which analyses the truth-tables of nodes in a circuit to list all such potential reconfigurable logic gates for a particular circuit. Technology mapping with these new logic gates (or standard-cells) leads to a better mapping in terms of area and delay. Experiments employing our methodology over EPFL benchmarks, show average improvements of around 13%, 16% and 11.5% in terms of area, number of edges and delay respectively as compared to the conventional CMOS-centric standard-cell based mapping. Download Paper (PDF; Only available from the DATE venue WiFi)
10:00		End of session