Date: Tuesday 10 March 2020
Time: 17:00 - 18:30
Location / Room: Bayard

Chair:
Wanli Chang, University of york, GB

Co-Chair:
Emmanuel Grolleau, ENSMA, FR

This session presents novel techniques for systems requiring adaptations. The papers in this session are including monitoring techniques to increase reactivity, considering weakly-hard constraints, extending previous cache persistence analyses from one core to several cores, and modeling data chains while latency bounds are ensured.

Time	Label	Presentation Title Authors
17:00	4.5.1	RELIABLE AND ENERGY-AWARE FIXED-PRIORITY (M,K)-DEADLINES ENFORCEMENT WITH STANDBY-SPARING Speaker: Linwei Niu, West Virginia State University, US Authors: Linwei Niu1 and Dakai Zhu2 1West Virginia State University, US; 2University of Texas at San Antonio, US Abstract For real-time computing systems, energy efficiency, Quality of Service, and fault tolerance are among the major design concerns. In this work, we study the problem of reliable and energy-aware fixed-priority (m,k)-deadlines enforcement with standby-sparing. The standby-sparing systems adopt a primary processor and a spare processor to provide fault tolerance for both permanent and transient faults. In order to reduce energy consumption for such kind of systems, we proposed a novel scheduling scheme under the QoS constraint of (m,k)-deadlines. The evaluation results demonstrate that our proposed approach significantly outperformed the previous research in energy conservation while assuring (m,k)-deadlines and fault tolerance for real-time systems. Download Paper (PDF; Only available from the DATE venue WiFi)
17:30	4.5.2	PERIOD ADAPTATION FOR CONTINUOUS SECURITY MONITORING IN MULTICORE REAL-TIME SYSTEMS Speaker: Monowar Hasan, University of Illinois at Urbana-Champaign, US Authors: Monowar Hasan1, Sibin Mohan2, Rodolfo Pellizzoni3 and Rakesh Bobba4 1University of Illinois at Urbana-Champaign, US; 2University of Illinois at Urbana-Champaign (UIUC), US; 3University of Waterloo, CA; 4Oregon State University, US Abstract We propose HYDRA-C, a design-time evaluation framework for integrating monitoring mechanisms in multicore real-time systems (RTS). Our goal is to ensure that security (or other monitoring) mechanisms execute in a "continuous" manner -- i.e., as often as possible, across cores. This is to ensure that any such mechanisms run with few interruptions, if any. HYDRA-C is intended to allow designers of RTS to integrate monitoring mechanisms without perturbing existing timing properties or execution orders. We demonstrate the framework using a proof-of-concept implementation with intrusion detection mechanisms as security tasks. We develop and use both, (a) a custom intrusion detection system (IDS) as well as (b) Tripwire -- an open source data integrity checking tool. We compare the performance of HYDRA-C with a state-of-the-art multicore RT security integration approach and find that our method does not impact the schedulability and, on average, can detect intrusions 19.05% faster without impacting the performance of RT tasks. Download Paper (PDF; Only available from the DATE venue WiFi)
18:00	4.5.3	EFFICIENT LATENCY BOUND ANALYSIS FOR DATA CHAINS OF REAL-TIME TASKS IN MULTIPROCESSOR SYSTEMS Speaker: Jiankang Ren, Dalian University of Technology, CN Authors: Jiankang Ren1, Xin He1, Junlong Zhou2, Hongwei Ge1, Guowei Wu1 and Guozhen Tan1 1Dalian University of Technology, CN; 2Nanjing University of Science and Technology, CN Abstract End-to-end latency analysis is one of the key problems in the automotive embedded system design. In this paper, we propose an efficient worst-case end-to-end latency analysis method for data chains of periodic real-time tasks executed on multiprocessors under a partitioned fixed-priority preemptive scheduling policy. The key idea of this research is to improve the analysis efficiency by transforming the problem of bounding the worst-case latency of the data chain to a problem of bounding the releasing interval of data propagation instances for each pair of consecutive tasks in the chain. In particular, we derive an upper bound on the releasing interval of successive data propagation instances to yield the desired data chain latency bound by a simple accumulation. Based on the above idea, we present an efficient latency upper bound analysis algorithm with polynomial time complexity. Experiments with randomly generated task sets based on a generic automotive benchmark show that our proposed approach can obtain a relatively tighter data chain latency upper bound with lower computational cost. Download Paper (PDF; Only available from the DATE venue WiFi)
18:15	4.5.4	CACHE PERSISTENCE-AWARE MEMORY BUS CONTENTION ANALYSIS FOR MULTICORE SYSTEMS Speaker: Syed Aftab Rashid, Polytechnic Institute of Porto, PT Authors: Syed Aftab Rashid, Geoffrey Nelissen and Eduardo Tovar, Polytechnic Institute of Porto, PT Abstract Memory bus contention strongly relates to the number of main memory requests generated by tasks running on different cores of a multicore platform, which, in turn, depends on the content of the cache memories during the execution of those tasks. Recent works have shown that due to cache persistence the memory access demand of multiple jobs of a task may not always be equal to its worst-case memory access demand in isolation. Analysis of the variable memory access demand of tasks due to cache persistence leads to significantly tighter worst-case response time (WCRT) of tasks. In this work, we show how the notion of cache persistence can be extended from single-core to multicore systems. In particular, we focus on analyzing the impact of cache persistence on the memory bus contention suffered by tasks executing on a multicore platform considering both work conserving and non-work conserving bus arbitration policies. Experimental evaluation shows that cache persistence-aware analyses of bus arbitration policies increase the number of task sets deemed schedulable by up to 70 percentage points in comparison to their respective counterparts that do not account for cache persistence Download Paper (PDF; Only available from the DATE venue WiFi)
18:30	IP2-7, 934	TOWARDS A MODEL-BASED MULTI-OBJECTIVE OPTIMIZATION APPROACH FOR SAFETY-CRITICAL REAL-TIME SYSTEMS Speaker: Emmanuel Grolleau, LIAS / ISAE-ENSMA, FR Authors: Soulimane Kamni1, Yassine OUHAMMOU2, Antoine Bertout3 and Emmanuel Grolleau4 1LIAS/ENSMA, FR; 2LIAS / ISAE-ENSMA, FR; 3LIAS, Université de Poitiers, ISAE-ENSMA, FR; 4LIAS, ISAE-ENSMA, Universite de Poitiers, FR Abstract In safety-critical real-time systems domain, obtaining the appropriate operational model which meets the temporal (e.g. deadlines) and business (e.g. redundancy) requirements while being optimal in terms of several metrics is a primordial process in the design life-cycle. Recently, several researches have proposed to explore cross-domain trade-offs for a higher behaviour performance. Indeed, this process represents the first step in the deployment phase, which is very sensitive because it could be error-prone and time consuming. This paper is a work in progress proposing an approach aiming to help real-time system architects to take benefit from existing works, overcome their limits, and capitalize the efforts. Furthermore, the approach is based on the model-driven engineering paradigm and suggests to ease the usage of methods and tools thanks to repositories gathering them as a sort of a shared knowledge. Download Paper (PDF; Only available from the DATE venue WiFi)
18:30		End of session