Date: Tuesday 10 March 2020
Time: 17:00 - 18:30
Location / Room: Autrans

Chair:
Dimitris Gizopoulos, UoA, GR

Co-Chair:
George Karakonstantis, Queen's University Belfast, GR

This session presents the results of three European Projects in different stages of execution covering the development of a complete synthesis and optimization methodology for nano-crossbar arrays; the reliability, security, and associated EDA tools for nanoelectronic systems, and the exploitation of STT-MTJ technologies for heterogeneous function implementation.

Time	Label	Presentation Title Authors
17:00	4.3.1	NANO-CROSSBAR BASED COMPUTING: LESSONS LEARNED AND FUTURE DIRECTIONS Speaker: Mustafa Altun, Istanbul TU, TR Authors: Mustafa Altun1, Ismail Cevik1, Ahmet Erten1, Osman Eksik1, Mircea Stan2 and Csaba Moritz3 1Istanbul TU, TR; 2University of Virginia, US; 3University of Massachusetts Amherst, US Abstract In this paper, we first summarize our research activities done through our European Union's Horizon-2020 project between 2015 and 2019. The project has a goal of developing synthesis and performance optimization techniques for nanocrossbar arrays. For this purpose, different computing models including diode, memristor, FET, and four-terminal switch based models, within different technologies including carbon nanotubes, nanowires, and memristors as well as the CMOS technology have been investigated. Their capabilities to realize logic functions and to tolerate faults have been deeply analyzed. From these experiences, we think that instead of replacing CMOS with a completely new crossbar based technology, developing CMOS compatible crossbar technologies and computing models is a more viable solution to overcome challenges in CMOS miniaturization. At this point, four terminal switch based arrays, called switching lattices, come forward with their CMOS compatibility feature as well as with their area efficient device and circuit realizations. We have showed that switching lattices can be efficiently implemented using a standard CMOS process to implement logic functions by doing experiments in a 65nm CMOS process. Further in this paper, we make an introduction of realizing memory arrays with switching lattices including ROMs and RAMs. Also we discuss challenges and promises in realizing switching lattices for under 30nm CMOS technologies including FinFET technologies. Download Paper (PDF; Only available from the DATE venue WiFi)
17:30	4.3.2	RESCUE: INTERDEPENDENT CHALLENGES OF RELIABILITY, SECURITY AND QUALITY IN NANOELECTRONIC SYSTEMS Speaker: Maksim Jenihhin, Tallinn University of Technology, EE Authors: Maksim Jenihhin1, Said Hamdioui2, Matteo Sonza Reorda3, Milos Krstic4, Peter Langendoerfer4, Christian Sauer5, Anton Klotz5, Michael Huebner6, Joerg Nolte6, H.T. Vierhaus6, Georgios Selimis7, Dan Alexandrescu8, Mottaqiallah Taouil2, Geert-Jan Schrijen7, Luca Sterpone3, Giovanni Squillero3, Zoya Dyka4 and Jaan Raik1 1Tallinn University of Technology, EE; 2TU Delft, NL; 3Politecnico di Torino, IT; 4Leibniz-Institut für innovative Mikroelektronik, DE; 5Cadence Design Systems, DE; 6BTU Cottbus-Senftenberg, DE; 7Intrinsic-ID, NL; 8IROC Technologies, FR Abstract The recent trends for nanoelectronic computing systems include machine-to-machine communication in the era of Internet-of-Things (IoT) and autonomous systems, complex safety-critical applications, extreme miniaturization of implementation technologies and intensive interaction with the physical world. These set tough requirements on mutually dependent extra-functional design aspects. The H2020 MSCA ITN project RESCUE is focused on key challenges for reliability, security and quality, as well as related electronic design automation tools and methodologies. The objectives include both research advancements and cross-sectoral training of a new generation of interdisciplinary researchers. Notable interdisciplinary collaborative research results for the first half-period include novel approaches for test generation, soft-error and transient faults vulnerability analysis, cross-layer fault-tolerance and error-resilience, functional safety validation, reliability assessment and run-time management, HW security enhancement and initial implementation of these into holistic EDA tools. Download Paper (PDF; Only available from the DATE venue WiFi)
18:00	4.3.3	A UNIVERSAL SPINTRONIC TECHNOLOGY BASED ON MULTIFUNCTIONAL STANDARDIZED STACK Speaker: Mehdi Tahoori, Karlsruhe Institute of Technology, DE Authors: Mehdi Tahoori1, Sarath Mohanachandran Nair1, Rajendra Bishnoi2, Lionel Torres3, Guillaume Partigeon4, Gregory DiPendina5 and Guillaume Prenat5 1Karlsruhe Institute of Technology, DE; 2TU Delft, NL; 3Université de Montpellier, FR; 4LIRMM, FR; 5Spintec, FR Abstract The goal of the GREAT RIA project is to co-integrate multiple functions like sensors ("Sensing"), RF emitters or receivers ("Communicating") and logic/memory ("Processing/Storing") together within CMOS by adapting the Spin-Transfer Torque Magnetic Tunnel Junction (STT-MTJ), elementary constitutive cell of the MRAM memories, to a single baseline technology. Based on the STT unique set of performances (non-volatility, high speed, infinite endurance and moderate read/write power), GREAT will achieve the same goal as heterogeneous integration of devices but in a much simpler way. This will lead to a unique STT-MTJ cell technology called Multifunctional Standardized Stack (MSS). This paper presents the lessons learned in the project from the technology, compact modeling, process design kit, standard cells, as well as memory and system level design evaluation and exploration. The proposed technology and toolsets are giant leaps towards heterogeneous integrated technology and architectures for IoT. Download Paper (PDF; Only available from the DATE venue WiFi)
18:30		End of session