Date: Tuesday 10 March 2020
Time: 14:30 - 16:00
Location / Room: Chamrousse

Chair:
Christian Pilato, Politecnico di Milano, IT

Co-Chair:
Luca Carloni, Columbia University, US

Accelerating Design Space Exploration efficiently is needed to optimize hardware accelerators. At high level, learning techniques can provide ways to either recognize previously synthesized kernels or to model the hidden dependences between synthesis directive costs and performances. At a lower level, speeding up RTL simulations based on data dependencies analysis can speed up one of the most time consuming steps.

Time	Label	Presentation Title Authors
14:30	3.2.1	EFFICIENT AND ROBUST HIGH-LEVEL SYNTHESIS DESIGN SPACE EXPLORATION THROUGH OFFLINE MICRO-KERNELS PRE-CHARACTERIZATION Authors: Zi Wang, Jianqi Chen and Benjamin Carrion Schaefer, University of Texas at Dallas, US Abstract This work proposes a method to accelerate the process of High-Level Synthesis (HLS) Design Space Exploration (DSE) by pre-characterizing micro-kernels offline and creating predictive models of these. HLS allows to generate different types of micro-architectures from the same untimed behavioral description. This is typically done by setting different combinations of synthesis options in the form or synthesis directives specified as pragmas in the code. This allows, e.g. to control how loops should be synthesized, arrays and functions. Unique combinations of these pragmas leads to micro-architectures with a unique area vs. performance/power trade-offs. The main problem is that the search space grows exponentially with the number of explorable operations. Thus, the main goal of efficient HLS DSE is to find the synthesis directives' combinations that lead to the Pareto-optimal designs quickly. Our proposed method is based on the pre-characterization of micro-kernels offline, creating predictive models for each of the kernels, and using the results to explore a new unseen behavioral description using compositional methods. In addition, we make use of perceptual hashing to match new unseen micro-kernels with the pre-characterized micro-kernels in order to further speed up the search process. Experimental results show that our proposed method is orders of magnitude faster than traditional methods. Download Paper (PDF; Only available from the DATE venue WiFi)
15:00	3.2.2	PROSPECTOR: SYNTHESIZING EFFICIENT ACCELERATORS VIA STATISTICAL LEARNING Speaker: Aninda Manocha, Princeton University, US Authors: Atefeh Mehrabi, Aninda Manocha, Benjamin Lee and Daniel Sorin, Duke University, US Abstract Accelerator design is expensive due to the effort required to understand an algorithm and optimize the design. Architects have embraced two technologies to reduce costs. High-level synthesis automatically generates hardware from code. Reconfigurable fabrics instantiate accelerators while avoiding fabrication costs for custom circuits. We further reduce design effort with statistical learning. We build an automated framework, called Prospector, that uses Bayesian techniques to optimize synthesis directives, reducing execution latency and resource usage in field-programmable gate arrays. We show in a certain amount of time designs discovered by Prospector are closer to Pareto-efficient designs compared to prior approaches. Download Paper (PDF; Only available from the DATE venue WiFi)
15:30	3.2.3	TANGO: AN OPTIMIZING COMPILER FOR JUST-IN-TIME RTL SIMULATION Speaker: Blaise-Pascal Tine, Georgia Tech, US Authors: Blaise Tine, Sudhakar Yalamanchili and Hyesoon Kim, Georgia Tech, US Abstract With Moore's law coming to an end, the advent of hardware specialization presents a unique challenge for a much tighter software and hardware co-design environment to exploit domain-specific optimizations and increase design efficiency. This trend is further accentuated by rapid-pace of innovations in Machine Learning and Graph Analytic, calling for a faster product development cycle for hardware accelerators and the importance of addressing the increasing cost of hardware verification. The productivity of software-hardware co-design relies upon a better integration between the software and hardware design methodologies, but more importantly in the effectiveness of the design tools and hardware simulators at reducing the development time. In this work, we developed Tango, an Optimizing compiler for a Just-in-Time RTL simulator. Tango implements unique hardware-centric compiler transformations to speed up runtime code generation in a software-hardware co-design environment where hardware simulation speed is critical. Tango achieves a 6x average speedup compared to the state-of-the-art RTL simulators. Download Paper (PDF; Only available from the DATE venue WiFi)
16:01	IP1-10, 728	POISONING THE (DATA) WELL IN ML-BASED CAD: A CASE STUDY OF HIDING LITHOGRAPHIC HOTSPOTS Speaker: Kang Liu, New York University, US Authors: Kang Liu, Benjamin Tan, Ramesh Karri and Siddharth Garg, New York University, US Abstract Machine learning (ML) provides state-of-the-art performance in many parts of computer-aided design (CAD) flows. However, deep neural networks (DNNs) are susceptible to various adversarial attacks, including data poisoning to compromise training to insert backdoors. Sensitivity to training data integrity presents a security vulnerability, especially in light of malicious insiders who want to cause targeted neural network misbehavior. In this study, we explore this threat in lithographic hotspot detection via training data poisoning, where hotspots in a layout clip can be "hidden" at inference time by including a trigger shape in the input. We show that training data poisoning attacks are feasible and stealthy, demonstrating a backdoored neural network that performs normally on clean inputs but misbehaves on inputs when a backdoor trigger is present. Furthermore, our results raise some fundamental questions about the robustness of ML-based systems in CAD. Download Paper (PDF; Only available from the DATE venue WiFi)
16:02	IP1-11, 667	SOLOMON: AN AUTOMATED FRAMEWORK FOR DETECTING FAULT ATTACK VULNERABILITIES IN HARDWARE Speaker: Milind Srivastava, IIT Madras, IN Authors: Milind Srivastava1, PATANJALI SLPSK1, Indrani Roy1, Chester Rebeiro1, Aritra Hazra2 and Swarup Bhunia3 1IIT Madras, IN; 2IIT Kharagpur, IN; 3University of Florida, US Abstract Fault attacks are potent physical attacks on crypto-devices. A single fault injected during encryption can reveal the cipher's secret key. In a hardware realization of an encryption algorithm, only a tiny fraction of the gates is exploitable by such an attack. Finding these vulnerable gates has been a manual and tedious task requiring considerable expertise. In this paper, we propose SOLOMON, the first automatic fault attack vulnerability detection framework for hardware designs. Given a cipher implementation, either at RTL or gate-level, SOLOMON uses formal methods to map vulnerable regions in the cipher algorithm to specific locations in the hardware thus enabling targeted countermeasures to be deployed with much lesser overheads. We demonstrate the efficacy of the SOLOMON framework using three ciphers: AES, CLEFIA, and Simon. Download Paper (PDF; Only available from the DATE venue WiFi)
16:02	IP1-12, 694	FORMAL SYNTHESIS OF MONITORING AND DETECTION SYSTEMS FOR SECURE CPS IMPLEMENTATIONS Speaker: Ipsita Koley, IIT Kharagpur, IN Authors: Ipsita Koley1, Saurav Kumar Ghosh1, Dey Soumyajit1, Debdeep Mukhopadhyay1, Amogh Kashyap K N2, Sachin Kumar Singh2, Lavanya Lokesh2, Jithin Nalu Purakkal2 and Nishant Sinha2 1IIT Kharagpur, IN; 2Robert Bosch Engineering and Business Solutions Private Limited, IN Abstract We consider the problem of securing a given control loop implementation of a cyber-physical system (CPS) in the presence of Man-in-the-Middle attacks on data exchange between plant and controller over a compromised network. To this end, there exists various detection schemes which provide mathematical guarantees against such attacks for the theoretical control model. However, such guarantees may not hold for the actual control software implementation. In this article, we propose a formal approach towards synthesizing attack detectors with varying thresholds which can prevent performance degrading stealthy attacks while minimizing false alarms. Download Paper (PDF; Only available from the DATE venue WiFi)
16:00		End of session