Date: Tuesday 10 March 2020
Time: 11:30 - 13:00
Location / Room: Stendhal

Chair:
Manuel Barragan, TIMA, FR

Co-Chair:
Haralampos Stratigopoulos, LIP6, FR

Producing reliable and secure analog circuits is a challenging task. This session addresses novel and systematic approaches to analog security, based on key sequencing, and analog design, from automatic netlist annotation to Bayesian modeling optimization.

Time	Label	Presentation Title Authors
11:30	2.4.1	GANA: GRAPH CONVOLUTIONAL NETWORK BASED AUTOMATED NETLIST ANNOTATION FOR ANALOG CIRCUITS Speaker: Kishor Kunal, University of Minnesota, IN Authors: Kishor Kunal1, Tonmoy Dhar2, Meghna Madhusudan2, Jitesh Poojary1, Arvind Sharma1, Wenbin Xu3, Steven Burns4, Jiang Hu3, Ramesh Harjani1 and Sachin S. Sapatnekar1 1University of Minnesota, US; 2University of Minnesota Twin Cities, US; 3Texas A&M University, US; 4Intel Corporation, US Abstract Automated subcircuit identification enables the creation of hierarchical representations of analog netlists, and can facilitate a variety of design automation tasks such as circuit layout and optimization. Subcircuit identification must be capable of navigating the numerous alternative structures that can implement any analog function, but traditional graph-based methods have been limited by the large number of such structural variants. The novel approach in this paper is based on the use of a trained graph convolutional neural network (GCN) that identifies netlist elements for circuit blocks at upper levels of the design hierarchy. Structures at lower levels of hierarchy are identified using graph-based algorithms. The proposed recognition scheme organically detects layout constraints, such as symmetry and matching, whose identification is essential for high-quality hierarchical layout. The subcircuit identification method demonstrates a high degree of accuracy over a wide range of analog designs, successfully identifies larger circuits that contain sub-blocks such as OTAs, LNAs, mixers, oscillators, and band-pass filters, and provides hierarchical decompositions of such circuits. Download Paper (PDF; Only available from the DATE venue WiFi)
12:00	2.4.2	SECURING PROGRAMMABLE ANALOG ICS AGAINST PIRACY Speaker: Mohamed Elshamy, Sorbonne Université, CNRS, LIP6, FR Authors: Mohamed Elshamy, Alhassan Sayed, Marie-Minerve Louerat, Amine Rhouni, Hassan Aboushady and Haralampos-G. Stratigopoulos, Sorbonne Université, CNRS, LIP6, FR Abstract In this paper, we demonstrate a security approach for the class of highly-programmable analog Integrated Circuits (ICs) that can be used as a countermeasure for unauthorized chip use and piracy. The approach relies on functionality locking, i.e. a lock mechanism is introduced into the design such that unless the correct key is provided the functionality breaks. We show that for highly-programmable analog ICs the programmable fabric can naturally be used as the lock mechanism. We demonstrate the approach on a multi-standard RF receiver with configuration settings of 64-bit words. Download Paper (PDF; Only available from the DATE venue WiFi)
12:30	2.4.3	AN EFFICIENT BAYESIAN OPTIMIZATION APPROACH FOR ANALOG CIRCUIT SYNTHESIS VIA SPARSE GAUSSIAN PROCESS MODELING Speaker: Biao He, Fudan University, CN Authors: Biao He1, Shuhan Zhang1, Fan Yang2, Changhao Yan1, Dian Zhou3 and Xuan Zeng1 1Fudan university, CN; 2Fudan University, CN; 3University of Texas at Dallas, US Abstract Bayesian optimization with Gaussian process models has been proposed for analog synthesis, since it is efficient for the optimizations of expensive black-box functions. However, the computational cost for training and prediction of Gaussian process models are $O(N^3)$ and $O(N^2)$, respectively, where $N$ is the number of data points. The overhead of the Gaussian process modeling would be not negligible as $N$ reaches a slightly large number. Recently, a Bayesian optimization approach using neural network has been proposed to address this problem. It reduces the computational cost of training/prediction of Gaussian process models to $O(N)$ and $O(1)$, respectively. However, it reduces the infinite-dimensional kernel in traditional Gaussian process to finite-dimensional kernel using neural network mapping. It could weaken the characterization ability of Gaussian process. In this paper, we propose a novel Bayesian optimization approach using Sparse Pseudo-input Gaussian process (SPGP). The idea is to select $M$ so-called inducing points out of $N$ data points and use the kernel function of the $M$ inducing points to approximate the kernel function of $N$ data points. The proposed approach can also reduce the computational cost of training/prediction to $O(N)$ and $O(1)$, respectively. However, the kernel of the proposed approach is still infinite-dimensional. It could provide similar characterization ability as the traditional Gaussian process. Several experiments were provided to demonstrate the efficiency of the proposed approach. Download Paper (PDF; Only available from the DATE venue WiFi)
13:00	IP1-4, 307	SYMMETRY-BASED A/M-S BIST (SYMBIST): DEMONSTRATION ON A SAR ADC IP Speaker: Antonios Pavlidis, Sorbonne Université, CNRS, LIP6, FR Authors: Antonios Pavlidis1, Marie-Minerve Louerat1, Eric Faehn2, Anand Kumar3 and Haralampos-G. Stratigopoulos1 1Sorbonne Université, CNRS, LIP6, FR; 2STMicroelectronics, FR; 3STMicroelectronics, IN Abstract In this paper, we propose a defect-oriented Built-In Self-Test (BIST) paradigm for analog and mixed-signal (A/MS) Integrated Circuits (ICs), called symmetry-based BIST (Sym-BIST). SymBIST exploits inherent symmetries into the design to generate invariances that should hold true only in defect-free operation. Violation of any of these invariances points to defect detection. We demonstrate SymBIST on a 65nm 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) IP by ST Microelectronics. SymBIST does notresult in any performance penalty, it incurs an area overhead of less than 5%, the test time equals about 16x the time to convert an analog input sample, it can be interfaced with a 2-pin digital access mechanism, and it covers the entire A/M-S part of the IP achieving a likelihood-weighted defect coverage higher than 85%. Download Paper (PDF; Only available from the DATE venue WiFi)
13:01	IP1-5, 476	RANGE CONTROLLED FLOATING-GATE TRANSISTORS: A UNIFIED SOLUTION FOR UNLOCKING AND CALIBRATING ANALOG ICS Speaker: Yiorgos Makris, University of Texas at Dallas, US Authors: Sai Govinda Rao Nimmalapudi, Georgios Volanis, Yichuan Lu, Angelos Antonopoulos, Andrew Marshall and Yiorgos Makris, University of Texas at Dallas, US Abstract Analog Floating-Gate Transistors (AFGTs) are commonly used to fine-tune the performance of analog integrated circuits (ICs) after fabrication, thereby enabling high yield despite component mismatch and variability in semiconductor manufacturing. In this work, we propose a methodology that leverages such AFGTs to also prevent unauthorized use of analog ICs. Specifically, we introduce a locking mechanism that limits programming of AFGTs to a range which is inadequate for achieving the desired analog performance. Accordingly, our solution entails a two-step unlock-&-calibrate process. In the first step, AFGTs must be programmed through a secret sequence of voltages within that range, called waypoints. Successfully following the waypoints unlocks the ability to program the AFGTs over their entire range. Thereby, in the second step, the typical AFGT-based post-silicon calibration process can be applied to adjust the performance of the IC within its specifications. Protection against brute-force or intelligent attacks attempting to guess the unlocking sequence is ensured through the vast space of possible waypoints in the continuous (analog) domain. Feasibility and effectiveness of the proposed solution is demonstrated and evaluated on an Operational Transconductance Amplifier (OTA). To our knowledge, this is the first solution which leverages the power of analog keys and addresses both unlocking and calibration needs of analog ICs in a unified manner. Download Paper (PDF; Only available from the DATE venue WiFi)
13:02	IP1-6, 699	TESTING THROUGH SILICON VIAS IN POWER DISTRIBUTION NETWORK OF 3D-IC WITH MANUFACTURING VARIABILITY CANCELLATION Speaker: Koutaro Hachiya, Teikyo Heisei University, JP Authors: Koutaro Hachiya1 and Atsushi Kurokawa2 1Teikyo Heisei University, JP; 2Hirosaki University, JP Abstract To detect open defects of power TSVs (Through Silicon Vias) in PDNs (Power Distribution Networks) of stacked 3D-ICs, a method was proposed which measures resistances between power micro-bumps connected to PDN and detects defects of TSVs by changes of the resistances. It suffers from manufacturing variabilities and must place one micro-bump directly under each TSV (direct-type placement style) to maximize its diagnostic performance, but the performance was not enough for practical applications. A variability cancellation method was also devised to improve the diagnostic performance. In this paper, a novel middle-type placement style is proposed which places one micro-bump between each pair of TSVs. Experimental simulations using a 3D-IC example show that the diagnostic performances of both the direct-type and the middle-type examples are improved by the variability cancellation and reach the practical level. The middle-type example outperforms the direct-type example in terms of number of micro-bumps and number of measurements. Download Paper (PDF; Only available from the DATE venue WiFi)
13:00		End of session