12.1 Special Day on "Silicon Photonics": Design Automation for Photonics

Time	Label	Presentation Title Authors
16:00	12.1.1	OPPORTUNITIES FOR CROSS-LAYER DESIGN IN HIGH-PERFORMANCE COMPUTING SYSTEMS WITH INTEGRATED SILICON PHOTONIC NETWORKS Speaker: Mahdi Nikdast, Colorado State University, US Authors: Asif Mirza, Shadi Manafi Avari, Ebadollah Taheri, Sudeep Pasricha and Mahdi Nikdast, Colorado State University, US Abstract With the ever growing complexity of high-performance computing (HPC) systems to satisfy emerging application requirements (e.g., high memory bandwidth requirement for machine learning applications), the performance bottleneck in such systems has moved from being computation-centric to be more communication-centric. Silicon photonic interconnection networks have been proposed to address the aggressive communication requirements in HPC systems, to realize higher bandwidth, lower latency, and better energy efficiency. There have been many successful efforts on developing silicon photonic devices, integrated circuits, and architectures for HPC systems. Moreover, many efforts have been made to address and mitigate the impact of different challenges (e.g., fabrication process and thermal variations) in silicon photonic interconnects. However, most of these efforts have focused only on a single design layer in the system design space (e.g., device, circuit or architecture level). Therefore, there is often a gap between what a design technique can improve in one layer, and what it might impair in another one. In this paper, we discuss the promise of cross-layer design methodologies for HPC systems integrating silicon photonic interconnects. In particular, we discuss how such cross-layer design solutions based on cooperatively designing and exchanging design objectives among different system design layers can help achieve the best possible performance when integrating silicon photonics into HPC systems. Download Paper (PDF; Only available from the DATE venue WiFi)
16:30	12.1.2	DESIGN AND VALIDATION OF PHOTONIC IP MACROS BASED ON FOUNDRY PDKS Authors: Ruping Cao, François Chabert and Pieter Dumon, Luceda Photonics, BE Abstract Silicon photonic foundry PDKs are steadily maturing. On the basis of these, designers can start to design and validate more complex circuits. Successful prototypes and productization depend however on a tight integration of the design flow, across hierarchical levels and between layout and simulation model extraction. Circuit performance and yield is impacted by fabrication variability and needs to be taken into account in the design cycle already at prototype level. We will show how a fully flow with integrated layout, circuit and building block simulation can speed up design and validation of larger photonic macros and discuss PDK requirements.
17:00	12.1.3	EFFICIENT OPTICAL POWER DELIVERY SYSTEM FOR HYBRID ELECTRONIC-PHOTONIC MANYCORE PROCESSORS Speaker: Jiang Xu, Hong Kong University of Science and Technology, HK Authors: Shixi Chen, Jiang Xu, Xuanqi Chen, Zhifei Wang, Jun Feng, Jiaxu Zhang, Zhongyuan Tian and Xiao Li, Hong Kong University of Science and Technology, HK Abstract A lot of efforts have been devoted to optically enabled high-performance communication infrastructures for future manycore processors. Silicon photonic network promises high bandwidth, high energy efficiency and low latency. However, the ever-increasing design complexity results in complex optical power demands, which stress the optical power delivery and affect delivery efficiency. Facing optical power delivery challenges, we propose a Ring- based Optical Active Delivery (ROAD) system, to effectively manage and efficiently deliver optical power throughout photonic-electronic hybrid systems. Download Paper (PDF; Only available from the DATE venue WiFi)
17:30		End of session

Time

Label

Presentation Title
Authors

16:00

12.1.1

OPPORTUNITIES FOR CROSS-LAYER DESIGN IN HIGH-PERFORMANCE COMPUTING SYSTEMS WITH INTEGRATED SILICON PHOTONIC NETWORKS
Speaker:
Mahdi Nikdast, Colorado State University, US
Authors:
Asif Mirza, Shadi Manafi Avari, Ebadollah Taheri, Sudeep Pasricha and Mahdi Nikdast, Colorado State University, US
Abstract
With the ever growing complexity of high-performance computing (HPC) systems to satisfy emerging application requirements (e.g., high memory bandwidth requirement for machine learning applications), the performance bottleneck in such systems has moved from being computation-centric to be more communication-centric. Silicon photonic interconnection networks have been proposed to address the aggressive communication requirements in HPC systems, to realize higher bandwidth, lower latency, and better energy efficiency. There have been many successful efforts on developing silicon photonic devices, integrated circuits, and architectures for HPC systems. Moreover, many efforts have been made to address and mitigate the impact of different challenges (e.g., fabrication process and thermal variations) in silicon photonic interconnects. However, most of these efforts have focused only on a single design layer in the system design space (e.g., device, circuit or architecture level). Therefore, there is often a gap between what a design technique can improve in one layer, and what it might impair in another one. In this paper, we discuss the promise of cross-layer design methodologies for HPC systems integrating silicon photonic interconnects. In particular, we discuss how such cross-layer design solutions based on cooperatively designing and exchanging design objectives among different system design layers can help achieve the best possible performance when integrating silicon photonics into HPC systems.
Download Paper (PDF; Only available from the DATE venue WiFi)

16:30

12.1.2

DESIGN AND VALIDATION OF PHOTONIC IP MACROS BASED ON FOUNDRY PDKS
Authors:
Ruping Cao, François Chabert and Pieter Dumon, Luceda Photonics, BE
Abstract
Silicon photonic foundry PDKs are steadily maturing. On the basis of these, designers can start to design and validate more complex circuits. Successful prototypes and productization depend however on a tight integration of the design flow, across hierarchical levels and between layout and simulation model extraction. Circuit performance and yield is impacted by fabrication variability and needs to be taken into account in the design cycle already at prototype level. We will show how a fully flow with integrated layout, circuit and building block simulation can speed up design and validation of larger photonic macros and discuss PDK requirements.

17:00

12.1.3

EFFICIENT OPTICAL POWER DELIVERY SYSTEM FOR HYBRID ELECTRONIC-PHOTONIC MANYCORE PROCESSORS
Speaker:
Jiang Xu, Hong Kong University of Science and Technology, HK
Authors:
Shixi Chen, Jiang Xu, Xuanqi Chen, Zhifei Wang, Jun Feng, Jiaxu Zhang, Zhongyuan Tian and Xiao Li, Hong Kong University of Science and Technology, HK
Abstract
A lot of efforts have been devoted to optically enabled high-performance communication infrastructures for future manycore processors. Silicon photonic network promises high bandwidth, high energy efficiency and low latency. However, the ever-increasing design complexity results in complex optical power demands, which stress the optical power delivery and affect delivery efficiency. Facing optical power delivery challenges, we propose a Ring- based Optical Active Delivery (ROAD) system, to effectively manage and efficiently deliver optical power throughout photonic-electronic hybrid systems.
Download Paper (PDF; Only available from the DATE venue WiFi)

17:30

End of session