11.6 Aging: estimation and mitigation

Time	Label	Presentation Title Authors
14:00	11.6.1	IMPACT OF NBTI AGING ON SELF-HEATING IN NANOWIRE FET Speaker: Hussam Amrouch, Karlsruhe Institute of Technology, DE Authors: Om Prakash¹, Hussam Amrouch¹, Sanjeev Kumar Manhas² and Joerg Henkel¹ ¹Karlsruhe Institute of Technology, DE; ²IIT Roorkee, IN Abstract This is the first work that investigates the impact of Negative Bias Temperature Instability (NBTI) on the Self-Heating (SH) phenomena in Silicon Nanowire Field-Effect Transistors (SiNW-FETs). We investigate the individual as well as joint impact of NBTI and SH on pSiNW-FETs and demonstrate that NBTI-induced traps mitigate SH effects due to reduced current densities. Our Technology CAD (TCAD)-based SiNW-FET device is calibrated against experimental data. It accounts for thermodynamic and hydrodynamic effects in 3-D nano structures for accurate modeling of carrier transport mechanisms. Our analysis focuses on how lattice temperature, thermal resistance and thermal capacitance of pSiNW-FETs are affected due to NBTI, demonstrating that accurate self-heating modeling necessitates considering the effects that NBTI aging has over time. Hence, NBTI and SH effects need to be jointly and not individually modeled. Our evaluation shows that an individual modeling of NBTI and SH effects leads to a noticeable overestimation of the overall induced delay increase in circuits due to the impact of NBTI traps on SH mitigation. Hence, it is necessary to model NBTI and SH effects jointly in order to estimate efficient (i.e. small, yet sufficient) timing guardbands that protect circuits against timing violations, which will occur at runtime due to delay increases induced by aging and self-heating. Download Paper (PDF; Only available from the DATE venue WiFi)
14:30	11.6.2	POWERPLANNINGDL: RELIABILITY-AWARE FRAMEWORK FOR ON-CHIP POWER GRID DESIGN USING DEEP LEARNING Speaker: Sukanta Dey, IIT Guwahati, IN Authors: Sukanta Dey, Sukumar Nandi and Gaurav Trivedi, IIT Guwahati, IN Abstract With the increase in the complexity of chip designs, VLSI physical design has become a time-consuming task, which is an iterative design process. Power planning is that part of the floorplanning in VLSI physical design where power grid networks are designed in order to provide adequate power to all the underlying functional blocks. Power planning also requires multiple iterative steps to create the power grid network while satisfying the allowed worst-case IR drop and Electromigration (EM) margin. For the first time, this paper introduces Deep learning (DL)-based framework to approximately predict the initial design of the power grid network, considering different reliability constraints. The proposed framework reduces many iterative design steps and speeds up the total design cycle. Neural Network-based multi-target regression technique is used to create the DL model. Feature extraction is done, and training dataset is generated from the floorplans of some of the power grid designs extracted from IBM processor. The DL model is trained using the generated dataset. The proposed DL-based framework is validated using a new set of power grid specifications (obtained by perturbing the designs used in the training phase). The results show that the predicted power grid design is closer to the original design with minimal prediction error (~2%). The proposed DL-based approach also improves the design cycle time significantly with a speedup of ~6X for standard power grid benchmarks Download Paper (PDF; Only available from the DATE venue WiFi)
15:00	11.6.3	AN EFFICIENT MILP-BASED AGING-AWARE FLOORPLANNER FOR MULTI-CONTEXT COARSE-GRAINED RUNTIME RECONFIGURABLE FPGAS Speaker: Carl Sechen, University of Texas at Dallas, US Authors: Bo Hu, Mustafa Shihab, Yiorgos Makris, Benjamin Carrion Schaefer and Carl Sechen, University of Texas at Dallas, US Abstract Shrinking transistor sizes are jeopardizing the reliability of runtime reconfigurable Field Programmable Gate Arrays (FPGAs), making them increasingly sensitive to aging effects such as Negative Bias Temperature Instability (NBTI). This paper introduces a reliability-aware floorplanner which is tailored to multi-context, coarse-grained, runtime reconfigurable architectures (CGRRAs) and seeks to extend their Mean Time to Failure (MTTF) by balancing the usage of processing elements (PEs). The proposed method is based on a Mixed Integer Linear Programming (MILP) formulation, the solution to which produces appropriately-balanced mappings of workload to PEs on the reconfigurable fabric, thereby mitigating aging-induced lifetime degradation. Results demonstrate that, as compared to the default reliability-unaware floorplanning solutions, the proposed method achieves an average MTTF increase of 2.5X without introducing any performance degradation. Download Paper (PDF; Only available from the DATE venue WiFi)
15:30	IP5-10, 119	DELAY SENSITIVITY POLYNOMIALS BASED DESIGN-DEPENDENT PERFORMANCE MONITORS FOR WIDE OPERATING RANGES Speaker: Ruikai Shi, Chinese Academy of Sciences, CN Authors: Ruikai Shi¹, Liang Yang² and Hao Wang² ¹Chinese Academy of Sciences / University of Chinese Academy of Sciences, CN; ²Loongson Technology Corporation Ltd., CN Abstract The downsizing of CMOS technology makes circuit performance more sensitive to on-chip parameter variations. Previous proposed design-dependent ring oscillator (DDRO) method provides an efficient way to monitor circuit performance at runtime. However, the linear delay sensitivity expression may be inadequate, especially in a wide range of operating conditions. To overcome it, a new design-dependent performance monitor (DDPM) method is proposed in this work, which formulates the delay sensitivity as high-order polynomials, makes it possible to accurately track the nonlinear timing behavior for wide operating ranges. A 28nm technology is used for design evaluation, and quite a low error rate is achieved in circuit performance monitoring comparison. Download Paper (PDF; Only available from the DATE venue WiFi)
15:31	IP5-11, 191	MITIGATION OF SENSE AMPLIFIER DEGRADATION USING SKEWED DESIGN Speaker: Daniel Kraak, TU Delft, NL Authors: Daniel Kraak¹, Mottaqiallah Taouil¹, Said Hamdioui¹, Pieter Weckx², Stefan Cosemans² and Francky Catthoor² ¹TU Delft, NL; ²IMEC, BE Abstract Designers typically add design margins to semiconductor memories to compensate for aging. However, the aging impact increases with technology downscaling, leading to the need for higher margins. This results into a negative impact on area, yield, performance, and power consumption. As an alternative, mitigation schemes can be developed to reduce such impact. This paper proposes a mitigation scheme for the memory's sense amplifier (SA); the scheme is based on creating a skew in the relative strengths of the SA's cross-coupled inverters during design. The skew is compensated by aging due to unbalanced workloads. As a result, the impact of aging on the SA is reduced. To validate the mitigation scheme, the degradation of the sense amplifier is analyzed for several workloads.The experimental results show that the proposed mitigation scheme reduces the degradation of the sense amplifier's critical figure-of-merit, the offset voltage, with up to 26%. Download Paper (PDF; Only available from the DATE venue WiFi)
15:30		End of session

Time

Label

Presentation Title
Authors

14:00

11.6.1

IMPACT OF NBTI AGING ON SELF-HEATING IN NANOWIRE FET
Speaker:
Hussam Amrouch, Karlsruhe Institute of Technology, DE
Authors:
Om Prakash¹, Hussam Amrouch¹, Sanjeev Kumar Manhas² and Joerg Henkel¹
¹Karlsruhe Institute of Technology, DE; ²IIT Roorkee, IN
Abstract
This is the first work that investigates the impact of Negative Bias Temperature Instability (NBTI) on the Self-Heating (SH) phenomena in Silicon Nanowire Field-Effect Transistors (SiNW-FETs). We investigate the individual as well as joint impact of NBTI and SH on pSiNW-FETs and demonstrate that NBTI-induced traps mitigate SH effects due to reduced current densities. Our Technology CAD (TCAD)-based SiNW-FET device is calibrated against experimental data. It accounts for thermodynamic and hydrodynamic effects in 3-D nano structures for accurate modeling of carrier transport mechanisms. Our analysis focuses on how lattice temperature, thermal resistance and thermal capacitance of pSiNW-FETs are affected due to NBTI, demonstrating that accurate self-heating modeling necessitates considering the effects that NBTI aging has over time. Hence, NBTI and SH effects need to be jointly and not individually modeled. Our evaluation shows that an individual modeling of NBTI and SH effects leads to a noticeable overestimation of the overall induced delay increase in circuits due to the impact of NBTI traps on SH mitigation. Hence, it is necessary to model NBTI and SH effects jointly in order to estimate efficient (i.e. small, yet sufficient) timing guardbands that protect circuits against timing violations, which will occur at runtime due to delay increases induced by aging and self-heating.
Download Paper (PDF; Only available from the DATE venue WiFi)

14:30

11.6.2

POWERPLANNINGDL: RELIABILITY-AWARE FRAMEWORK FOR ON-CHIP POWER GRID DESIGN USING DEEP LEARNING
Speaker:
Sukanta Dey, IIT Guwahati, IN
Authors:
Sukanta Dey, Sukumar Nandi and Gaurav Trivedi, IIT Guwahati, IN
Abstract
With the increase in the complexity of chip designs, VLSI physical design has become a time-consuming task, which is an iterative design process. Power planning is that part of the floorplanning in VLSI physical design where power grid networks are designed in order to provide adequate power to all the underlying functional blocks. Power planning also requires multiple iterative steps to create the power grid network while satisfying the allowed worst-case IR drop and Electromigration (EM) margin. For the first time, this paper introduces Deep learning (DL)-based framework to approximately predict the initial design of the power grid network, considering different reliability constraints. The proposed framework reduces many iterative design steps and speeds up the total design cycle. Neural Network-based multi-target regression technique is used to create the DL model. Feature extraction is done, and training dataset is generated from the floorplans of some of the power grid designs extracted from IBM processor. The DL model is trained using the generated dataset. The proposed DL-based framework is validated using a new set of power grid specifications (obtained by perturbing the designs used in the training phase). The results show that the predicted power grid design is closer to the original design with minimal prediction error (~2%). The proposed DL-based approach also improves the design cycle time significantly with a speedup of ~6X for standard power grid benchmarks
Download Paper (PDF; Only available from the DATE venue WiFi)

15:00

11.6.3

AN EFFICIENT MILP-BASED AGING-AWARE FLOORPLANNER FOR MULTI-CONTEXT COARSE-GRAINED RUNTIME RECONFIGURABLE FPGAS
Speaker:
Carl Sechen, University of Texas at Dallas, US
Authors:
Bo Hu, Mustafa Shihab, Yiorgos Makris, Benjamin Carrion Schaefer and Carl Sechen, University of Texas at Dallas, US
Abstract
Shrinking transistor sizes are jeopardizing the reliability of runtime reconfigurable Field Programmable Gate Arrays (FPGAs), making them increasingly sensitive to aging effects such as Negative Bias Temperature Instability (NBTI). This paper introduces a reliability-aware floorplanner which is tailored to multi-context, coarse-grained, runtime reconfigurable architectures (CGRRAs) and seeks to extend their Mean Time to Failure (MTTF) by balancing the usage of processing elements (PEs). The proposed method is based on a Mixed Integer Linear Programming (MILP) formulation, the solution to which produces appropriately-balanced mappings of workload to PEs on the reconfigurable fabric, thereby mitigating aging-induced lifetime degradation. Results demonstrate that, as compared to the default reliability-unaware floorplanning solutions, the proposed method achieves an average MTTF increase of 2.5X without introducing any performance degradation.
Download Paper (PDF; Only available from the DATE venue WiFi)

15:30

IP5-10, 119

DELAY SENSITIVITY POLYNOMIALS BASED DESIGN-DEPENDENT PERFORMANCE MONITORS FOR WIDE OPERATING RANGES
Speaker:
Ruikai Shi, Chinese Academy of Sciences, CN
Authors:
Ruikai Shi¹, Liang Yang² and Hao Wang²
¹Chinese Academy of Sciences / University of Chinese Academy of Sciences, CN; ²Loongson Technology Corporation Ltd., CN
Abstract
The downsizing of CMOS technology makes circuit performance more sensitive to on-chip parameter variations. Previous proposed design-dependent ring oscillator (DDRO) method provides an efficient way to monitor circuit performance at runtime. However, the linear delay sensitivity expression may be inadequate, especially in a wide range of operating conditions. To overcome it, a new design-dependent performance monitor (DDPM) method is proposed in this work, which formulates the delay sensitivity as high-order polynomials, makes it possible to accurately track the nonlinear timing behavior for wide operating ranges. A 28nm technology is used for design evaluation, and quite a low error rate is achieved in circuit performance monitoring comparison.
Download Paper (PDF; Only available from the DATE venue WiFi)

15:31

IP5-11, 191

MITIGATION OF SENSE AMPLIFIER DEGRADATION USING SKEWED DESIGN
Speaker:
Daniel Kraak, TU Delft, NL
Authors:
Daniel Kraak¹, Mottaqiallah Taouil¹, Said Hamdioui¹, Pieter Weckx², Stefan Cosemans² and Francky Catthoor²
¹TU Delft, NL; ²IMEC, BE
Abstract
Designers typically add design margins to semiconductor memories to compensate for aging. However, the aging impact increases with technology downscaling, leading to the need for higher margins. This results into a negative impact on area, yield, performance, and power consumption. As an alternative, mitigation schemes can be developed to reduce such impact. This paper proposes a mitigation scheme for the memory's sense amplifier (SA); the scheme is based on creating a skew in the relative strengths of the SA's cross-coupled inverters during design. The skew is compensated by aging due to unbalanced workloads. As a result, the impact of aging on the SA is reduced. To validate the mitigation scheme, the degradation of the sense amplifier is analyzed for several workloads.The experimental results show that the proposed mitigation scheme reduces the degradation of the sense amplifier's critical figure-of-merit, the offset voltage, with up to 26%.
Download Paper (PDF; Only available from the DATE venue WiFi)

15:30

End of session