7.8 22FDX - the superior technology for IoT, RF, Automotive and Mobility: Advanced Design Methodologies for Ultra-low Power Solutions

Serving the new trend in semiconductor industries to connect everything with everything, computing power does not matter as much as low leakage and/or low dynamic power at low cost.

GLOBALFOUNDRIES offers a technology with less complexity than FinFET, same gate length scaling enabled by fully-depleted channels, but with additional features like back-gate biasing which perfectly suits the IoT market needs.

Back-biasing is unique to FDSOI technologies and provides an additional degree of freedom to circuit and chip designers. Prominent examples for back-biasing utilization are extremely low Vdd operation and chip-level global corner trimming, static by OTP or eFuse as well as dynamic for power and temperature compensation.

This talk will give an overview on technology capabilities and features.

GLOBALFOUNDRIES 22FDX technology offers body biasing as a new optimization tool for designers to optimize power performance and area of their circuit. GLOBALFOUNDRIES and its IP eco-system partners have collaborated to develop a design platform that enables designers to take full advantage of these technology capabilities for low voltage IoT all the way to mobile application processor designs.

The talk will present benchmark implementation results that demonstrate the benefits of the 22FDX design platform for IoT and mobile application processor design points.

GLOBALFOUNDRIES' design guidelines and reference flows help the designer to easily adopt the 22FDX design platform. The talk will walk through the 22FDX specifics of the digital design flow and point out how to implement a digital design using body bias. 

One of the hottest buzzwords today is big data, i.e. the massive amounts of data that are produced by an ever expanding number of sensors across disciplines from archaeology to soccer. Some examples: in 2016, the amount of data transmitted globally for the first time exceeded a Zettabyte (10²¹), using up about 10% of the world energy supply. In 2015, the number of image sensors has risen above the number of humans on earth.

Thus, there is a need for dedicated data processing/machine learning chips that handle this load automatedly and reduce it to a data extract usable by humans. Deployment of these chips can be anywhere along the processing chain, e.g. integrated with the sensor interface to reduce data load at the source or as data aggregator in a server farm.

Prof. Mayr will give an overview of the multi-processor systems-on-chip (MPSoC) and sensor interfacing developed at his chair. As some of the first MPSoCs in 22nm FDSOI which use adaptive body biasing to compensate for process variability, they operate as low as 0.4V. Through a combination of dedicated accelerators (e.g. for machine learning) and conventional CPUs, these MPSoCs achieve an optimal compromise between energy efficiency and configurability. Applications pursued at the chair include: sensor nodes for the tactile internet, autonomous driving, neural implants and brain simulation.

Co-authors: Pasquale Davide Schiavone¹, Davide Rossi², Antonio Pullini¹, Francesco Conti^1,2, Frank K. Gurkaynak¹, Luca Benini^1,2
1. Integrated System laboratory, ETH, Zurich, Switzerland; 2. Energy Efficient Embedded Systems Laboratory, University Of Bologna, Bologna, Italy

An increasing number of end-node IoT applications require high performance and extreme energy efficiency to deal with the high computational requirements of near-sensor data analytics algorithms, within a power envelope of few milliWatts for long battery lifetime. A significant improvement of energy efficiency for digital computing systems can be achieved exploiting near-threshold operation. We present Quentin: a near-threshold SoC based on the open-source PULPissimo architecture, implemented in 22nm FDX technology. The proposed SoC is built around a 32-bit RISC-V core "RISCY" optimized for energy efficient digital signal processing, 512 kByte of L2 memory, and an autonomous I/O subsystem featuring an IO DMA coupled with a standard set of peripherals. RISCY features a 32-bit, 4-stages in-order pipeline implementing the RV32IMFC RISC-V ISA plus domain-specific extensions for near-sensor data analytics such as packed-SIMD (additions, comparisons, logic, shuffle and dot product), bit manipulation, hardware loops, etc. This talk will present the implementation of the SoC in 22nm FDX, featuring an area of 2 mm², a maximum operating frequency of 170 MHz (SSG, 0.59V, -40 C) and an estimated power consumption of 5 mW.