Date: Tuesday 20 March 2018
Time: 17:00 - 18:30
Location / Room: Konf. 2
Chair:
Vasilis Pavlidis, University of Manchester, GB
Co-Chair:
Giorgios Karakonstantis, Queen's University Belfast, GB
The session illustrates novel approaches to lower the high voltage and timing guard-bands affecting the performance of computing systems. The first talk introduces a methodology to increase the resiliency towards timing errors at ultra-low-voltages. Then, the placement of the timing monitor infrastructure is investigated in the second talk. The illustration of a mechanism to reliably tune the voltage supply concludes the session.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 17:00 | 4.4.1 | (Best Paper Award Candidate) TRIDENT: A COMPREHENSIVE TIMING ERROR RESILIENT TECHNIQUE AGAINST CHOKE POINTS AT NTC Speaker: Aatreyi Bal, Utah State University, US Authors: Aatreyi Bal, Sanghamitra Roy and Koushik Chakraborty, Utah State University, US Abstract Near Threshold Computing (NTC) systems have been inherently plagued with heightened process variation (PV) sensitivity. Choke points are an intriguing manifestation of this PV sensitivity. In this paper, we explore the probability of minimum timing violations, caused by choke points, in an NTC system and, their non-trivial impacts on the system reliability. We show that conventional timing error mitigation techniques are inefficient in tackling choke point induced minimum timing violations. Consequently, we propose a comprehensive error mitigation technique, Trident, to tackle choke points, at NTC. Trident offers a 1.37× performance improvement and a 1.1× energy efficiency gain over Razor at NTC, with minimal overheads. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 17:30 | 4.4.2 | BAYESIAN THEORY BASED SWITCHING PROBABILITY CALCULATION METHOD OF CRITICAL TIMING PATH FOR ON-CHIP TIMING SLACK MONITORING Speaker: Byung Su Kim, Samsung Electronics, Foundry, KR Authors: Byung Su Kim1 and Joon-Sung Yang2 1Samsung Electronics, KR; 2Sungkyunkwan University, KR Abstract Accurate in-situ monitoring is urgently required for an adaptive performance control system and post silicon validation. For accurate in-situ monitoring, a direct probing method is presented in which monitors directly measure a path delay from real critical timing paths. However, we may not be able to predict when the timing slack monitors would activate since the activation depends on a design structure and input patterns. If a timing slack monitor is rarely activated by timing critical paths, the observability from this monitor would be low and the monitor possibly can be discarded. For this reason, we propose a novel timing slack monitoring methodology based on switching probability of timing critical paths. Switching probability and correlation on critical timing paths are formulated, and the proposed method finds a list of critical path endpoints for the timing slack monitor insertion under given power and area constraints. Experimental results with ISCAS'89 circuits show that, compared to the method which places monitors for all worst critical paths, 16.67 ~ 97.2% of timing slack monitors are removed and 32.56 ~ 96.88% of dynamic power reduction from the monitors is achieved by the proposed method. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 18:00 | 4.4.3 | PERFORMANCE BASED TUNING OF AN INDUCTIVE INTEGRATED VOLTAGE REGULATOR DRIVING A DIGITAL CORE AGAINST PROCESS AND PASSIVE VARIATIONS Speaker: Venkata Chaitanya Krishna Chekuri, Georgia Institute of Technology, US Authors: Venkata Chaitanya Krishna Chekuri, Monodeep Kar, Arvind Singh and Saibal Mukhopadhyay, Georgia Institute of Technology, US Abstract This paper presents an auto-tuning method for fully integrated voltage regulators (IVRs) driving digital cores against variations in passive as well as process/temperature of the core. The key contribution is to perform auto-tuning of the coefficients of the feedback loop of the IVR based on the performance of the digital cores. Simulations using a high-frequency IVR Simulink model and digital logic in 45nm CMOS process shows that the proposed performance driven auto-tuning demonstrates potential for up to 12% increase in system performance under inductance and threshold variation. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 18:30 | IP1-14, 686 | INDUSTRIAL EVALUATION OF TRANSITION FAULT TESTING FOR COST EFFECTIVE OFFLINE ADAPTIVE VOLTAGE SCALING Speaker: Mahroo Zandrahimi, TU Delft, NL Authors: Mahroo Zandrahimi1, Philippe Debaud2, Armand Castillejo2 and Zaid Al-Ars1 1Delft University of Technology, NL; 2STMicroelectronics, FR Abstract Adaptive voltage scaling (AVS) has been used widely to compensate for process, voltage, and temperature variations as well as power optimization of integrated circuits. The current industrial state-of-the-art AVS approaches using Process Monitoring Boxes (PMBs) have shown several limitations such as huge characterization effort, which makes these approaches very expensive, and a low accuracy that results in extra margins, which consequently lead to yield loss and performance limitations. To overcome those limitations, in this paper we propose an alternative solution using transition fault test patterns, which is able to eliminate the need for PMBs, while improving the accuracy of voltage estimation. The paper shows, using simulation of ISCAS'99 benchmarks with 28nm FD-SOI library, that AVS using transition fault testing (TF-based AVS) results in an error as low as 5.33%. The paper also shows that the PMB approach can only account for 85% of the uncertainty in voltage measurements, which results in power waste, while the TF-based approach can account for 99% of that uncertainty. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 18:31 | IP1-15, 693 | AN ANALYSIS ON RETENTION ERROR BEHAVIOR AND POWER CONSUMPTION OF RECENT DDR4 DRAMS Speaker: Deepak M. Mathew, University of Kaiserslautern, DE Authors: Deepak M. Mathew1, Martin Schultheis1, Carl C. Rheinländer1, Chirag Sudarshan1, Matthias Jung2, Christian Weis1 and Norbert Wehn1 1University of Kaiserslautern, DE; 2Fraunhofer IESE, DE Abstract DRAM technology is scaling aggressively that results in high leakage power, worse data retention time behavior, and large process variations. Due to these process variations, vendors provide large guard bands on various DRAM currents and timing specifications that are over pessimistic. Detailed knowledge on the DRAM retention behavior and currents for the average case allow to improve memory system performance and energy efficiency of specific applications by moving away from worst case behavior. In this paper, we present an advanced measurement platform to investigate off-the-shelf DDR4 DRAMs' retention behavior, and to precisely measure various DRAM currents (IDDs and IPPs) at a wide range of operating temperatures. Error Checking and Correction (ECC) schemes are popular in correcting randomly scattered single bit errors. Since retention failures also occur randomly, ECCs can be used to improve DRAM retention behavior. Therefore, for the first time, we show the influence of ECC on the retention behavior of recent DDR4 DRAMs, and how it varies across various DRAM architectures considering detailed structure of the DRAM (true-cell devices / mixed-cell devices). Download Paper (PDF; Only available from the DATE venue WiFi) |
| 18:30 | End of session Exhibition Reception in Exhibition Area The Exhibition Reception will take place on Tuesday in the exhibition area, where free drinks for all conference delegates and exhibition visitors will be offered. All exhibitors are welcome to also provide drinks and snacks for the attendees. |