Date: Thursday 22 March 2018
Time: 14:00 - 15:30
Location / Room: Konf. 3
Chair:
Martin Trefzer, University of York, GB
Co-Chair:
Lukas Sekanina, University of Brno, CZ
The first two presentations cover applications for microfluidic devices. The first one considers sample preparation, i.e. how to efficiently prepare certain dilutions and mixtures of fluids with a given amount of storages. The second one considers programmable versions of these devices that allow for the realization of general purpose applications. The last two presentations introduce new circuit structures for computing technologies that rely on approximation and probabilities. More precisely, an adaptive approximated divider design and manipulating circuits for stochastic computing are presented.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 14:00 | 11.5.1 | STORAGE-AWARE SAMPLE PREPARATION USING FLOW-BASED MICROFLUIDIC LAB-ON-CHIP Speaker: Robert Wille, Institute for Integrated Circuits, Johannes Kepler University Linz, 4040 Linz, Austria, AT Authors: Sukanta Bhattacharjee1, Robert Wille2, Juinn-Dar Huang3 and Bhargab Bhattacharya1 1Indian Statistical Institute, Kolkata, IN; 2Johannes Kepler University Linz, AT; 3National Chiao Tung University,Hsinchu, TW Abstract Recent advances in microfluidics have been the major driving force behind the ubiquity of Labs-on-Chip (LoC) in biochemical protocol automation. The preparation of dilutions and mixtures of fluids is a basic step in sample preparation for which several algorithms and chip-architectures are well known. Dilution and mixing are implemented on biochips through a sequence of basic fluid-mixing and splitting operations performed in certain ratios. These steps are abstracted using a mixing graph. During this process, on-chip storage-units are needed to store intermediate fluids to be used later in the sequence. This allows to optimize the reactant-costs, to reduce the sample-preparation time, and/or to achieve the desired ratio. However, the number of storage-units is usually limited in given LoC architectures. Since this restriction is not considered by existing methods for sample preparation, the results that are obtained are often found to be useless (in the case when more storage-units are required than available) or more expensive than necessary (in the case when storage-units are available but not used, e.g., to further reduce the number of mixing operations or reactant-cost). In this paper, we present a storage-aware algorithm for sample preparation with flow-based LoCs which addresses these issues. We present a SAT-based approach to construct a mixing graph that enables the best usage of available storage-units while optimizing sample-preparation cost and/or time. Experimental results on several test cases reveal the scope, effectiveness, and the flexibility of the proposed method. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 14:30 | 11.5.2 | PUMP-AWARE FLOW ROUTING ALGORITHM FOR PROGRAMMABLE MICROFLUIDIC DEVICES Speaker: Tsung-Yi Ho, National Tsing Hua University, TW Authors: Guan-Ru Lai1, Chun-Yu Lin2 and Tsung-Yi Ho2 1TSMC, TW; 2National Tsing Hua University, TW Abstract As the biochemical experiment becomes more complicated and more diverse, the process of developing a specific-purpose microfluidic biochip for a new task can be very expensive and time consuming. Therefore, the programmable microfluidic devices (PMDs) are proposed as general purpose devices which can perform multiple functions without any hardware modification. Because the PMDs are controlled by pure software program, the assays can be done in parallel and the total completion time can be reduced. However, the high parallelism may cause congestion problem as different reagents are not allowed to cross each other to avoid unexpected mixing. Moreover, since reagents are pushed by the off-chip pump, the free channel from an off-chip pump to the actuated reagent is also prohibited to pass through. This could further complicate the congestion problem and increase the assay completion time significantly. However, some vulnerable reagents may spoil over time during the experiment. For timing critical application, it is indispensable to ensure the total assay completion time is within an upper limit. Therefore, we propose a pump-aware flow routing algorithm which deals with the complex routing congestion while minimizing the assay completion time within an upper limit Download Paper (PDF; Only available from the DATE venue WiFi) |
| 15:00 | 11.5.3 | ADAPTIVE APPROXIMATION IN ARITHMETIC CIRCUITS: A LOW-POWER UNSIGNED DIVIDER DESIGN Speaker: Honglan Jiang, University of Alberta, CA Authors: Honglan Jiang1, Leibo Liu2, Fabrizio Lombardi3 and Jie Han1 1University of Alberta, CA; 2Tsinghua University, CN; 3Northeastern University, US Abstract Many approximate arithmetic circuits have been proposed for high-performance and low-power applications. However, most designs are either hardware-fficient with a low accuracy or very accurate with a limited hardware saving, mostly due to the use of a static approximation. In this paper, an adaptive approximation approach is proposed for the design of a divider. In this design, division is computed by using a reduced-width divider and a shifter by adaptively pruning the input bits. Specifically, for a 2n/n division 2k/k bits are selected starting from the most significant '1' in the dividend/divisor. At the same time, redundant least significant bits (LSBs) are truncated or if the number of remaining LSBs is smaller than 2k for the dividend or k for the divisor, '0's are appended to the LSBs of the input. To avoid overflow, a 2(k+1)/(k+1) divider is used to compute the division of the 2k-bit dividend and the k-bit divisor, both with the most significant bit being '0'. Thus, k<n is a key variable that determines the size of the divider and the accuracy of the approximate design. Finally, an error correction circuit is proposed to recover the error caused by the shifter by using OR gates. The synthesis results in an industrial 28nm CMOS process show that the proposed 16/8 approximate divider using an 8/4 accurate divider is 2.5x as fast and consumes 34.42% of the power of the accurate 16/8 design. Compared with the other approximate dividers, the proposed design is significantly more accurate at a similar power-delay product. Moreover, simulation results show that the proposed approximate divider outperforms the other designs in two image processing applications. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 15:15 | 11.5.4 | CORRELATION MANIPULATING CIRCUITS FOR STOCHASTIC COMPUTING Speaker: Vincent Lee, University of Washington, US Authors: Vincent T. Lee, Armin Alaghi and Luis Ceze, University of Washington, US Abstract Stochastic computing (SC) is an emerging computing technique that promises high density, low power, and error tolerant solutions. In SC, values are encoded as unary bitstreams and SC arithmetic circuits operate on one or more bitstreams. In many cases, the input bitstreams must be correlated or uncorrelated for SC arithmetic to produce accurate results. As a result, a key challenge for designing SC accelerators is manipulating the impact of correlation across SC operations. This paper presents and evaluates a set of novel correlation manipulating circuits to manage correlation in SC computation: a synchronizer, desynchronizer, and decorrelator. We then use these circuits to propose improved SC maximum, minimum, and saturating adder designs. Compared to existing correlation manipulation techniques, our circuits are more accurate and up to 3x more energy efficient. In the context of an image processing pipeline, these circuits can reduce the total energy consumption by up to 24%. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 15:30 | IP5-6, 637 | FAULT-TOLERANT VALVE-BASED MICROFLUIDIC ROUTING FABRIC FOR DROPLET BARCODING IN SINGLE-CELL ANALYSIS Speaker: Yasamin Moradi, Technical University of Munich (TUM), DE Authors: Yasamin Moradi1, Mohamed Ibrahim2, Krishnendu Chakrabarty2 and Ulf Schlichtmann1 1Technical University of Munich, DE; 2Duke University, US Abstract High-throughput single-cell genomics is used to gain insights into diseases such as cancer. Motivated by this important application, microfluidics has emerged as a key technology for developing comprehensive biochemical procedures for studying DNA, RNA, proteins, and many other cellular components. Recently, a hybrid microfluidic platform has been proposed to efficiently automate the analysis of a heterogeneous sequence of cells. In this design, a valve-based routing fabric based on transposers is used to label/barcode the target cells. However, the design proposed in prior work overlooked defects that are likely to occur during chip fabrication and system integration. We address the above limitation by investigating the fault tolerance of the valve-based routing fabric. We develop a theory of failure assessment and introduce a design technique for achieving fault tolerance. Simulation results show that the proposed method leads to a slight increase in the fabric size and decrease in cell-analysis throughput, but this is only a small price to pay for the added assurance of fault tolerance in the new design. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 15:31 | IP5-7, 408 | OPTIMIZING POWER-ACCURACY TRADE-OFF IN APPROXIMATE ADDERS Speaker: Celia Dharmaraj, Indian Institute of Technology Madras, IN Authors: Celia Dharmaraj, Vinita Vasudevan and Nitin Chandrachoodan, Indian Institute of Technology Madras, IN Abstract Approximate circuit design has gained significance in recent years targeting applications like media processing where full accuracy is not required. In this paper, we propose an approximate adder in which the approximate part of the sum is obtained by finding a single optimal level that minimizes the mean error distance. Therefore hardware needed for the approximate part computation can be removed, which effectively results in very low power consumption. We compare the proposed adder with various approximate adders in the literature in terms of power and accuracy metrics. The power savings of our adder is shown to be 17% to 55% more than power savings of the existing approximate adders over a significant range of accuracy values. Further, in an image addition application, this adder is shown to provide the best trade-off between PSNR and power. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 15:30 | End of session Coffee Break in Exhibition Area
On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area (Terrace Level of the ICCD). Lunch Breaks (Großer Saal + Saal 1)On all conference days (Tuesday to Thursday), a seated lunch (lunch buffet) will be offered in the rooms "Großer Saal" and "Saal 1" (Saal Level of the ICCD) to fully registered conference delegates only. There will be badge control at the entrance to the lunch break area. Tuesday, March 20, 2018
Wednesday, March 21, 2018
Thursday, March 22, 2018
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