Date: Thursday 30 March 2017
Time: 08:30 - 10:00
Location / Room: 3B
Chair:
Marina Zapater Sancho, EPFL, CH
Co-Chair:
Giovanni Ansaloni, USI, CH
This session sets highlights on the impact of temperature and variability sources at the overall system level. Firstly, an approach that incorporates leakage in thermal simulations is presented and a thermal simulation framework is devised. After that, temperature is not only estimated but also minimized in the context of global interconnects by means of an analytic methodology. Finally, timing variability plays its role in the session and its effects in variable-latency designs.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 08:30 | 9.7.1 | (Best Paper Award Candidate) AN EFFICIENT LEAKAGE-AWARE THERMAL SIMULATION APPROACH FOR 3D-ICS USING CORRECTED LINEARIZED MODEL AND ALGEBRAIC MULTIGRID Speaker: Chao Yan, Microelectronics Dept., Fudan University, CN Authors: Chao Yan1, Hengliang Zhu1, Dian Zhou2 and Xuan Zeng1 1Fudan University, CN; 2University of Texas at Dallas, US Abstract Thermal control has become a great challenge for 3D-ICs due to the ever increasing power density and 3D integration. Among techniques to address the problem, fast thermal simulation approach is basically required to accurately characterize the runtime temperature variations of 3D-ICs. In this paper, we propose an accurate and fast leakage-aware thermal simulation approach for 3D-ICs with consideration of both heatsink cooling and microfluidic cooling. First, the proposed approach is based on a corrected linearized model for leakage power approximation, which is proved to be equivalent to the Newton-Chord method for solving nonlinear algebra equations. A convergence comparison is presented in this paper to show that such approach is more efficient than other methods for leakage-aware thermal simulation. Second, an aggregationbased algebraic multigrid (AMG) preconditioned iterative linear solver is adopted that greatly reduces the computation time for solving the linear equations during calculation, which makes the proposed approach even more efficient. Numerical experiments show that the proposed approach can achieve 8x-139x speedup in comparison with the state-of-the-art methods, and with almost negligible average temperature error no more than 0.025K and maximum temperature error no more than 0.095K. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 09:00 | 9.7.2 | A THERMALLY-AWARE ENERGY MINIMIZATION METHODOLOGY FOR GLOBAL INTERCONNECTS Speaker: Afzali Kusha, Tehran University, IR Authors: Soheil Nazar Shahsavani1, Alireza Shafaei Bejestan1, Shahin Nazarian1 and Massoud Pedram2 1University of Southern California, US; 2USC, US Abstract As a result of the Temperature Effect Inversion (TEI) in FinFET-based designs, gate delays decrease with the increase of temperature. In contrast, the resistive characteristic and hence delay of global interconnects increase with the temperature. However, as shown in this paper, if buffers are judiciously inserted in global interconnects, the buffer delay decrease is more pronounced than the interconnect delay increase, resulting in an overall performance improvement at higher temperatures. More specifically, this work models the delay of buffer-inserted global interconnects vs. temperature in order to derive the optimal number and size of buffers for a given interconnect length and temperature. Furthermore, the paper addresses the problem of minimizing the buffered interconnect energy consumption by changing the supply voltage level or FinFET threshold voltage, and also presents a temperature-aware optimization policy for solving this problem. Simulation results show average interconnect energy savings of 16% with no performance penalty for five different benchmarks implemented on a 14nm FinFET technology. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 09:30 | 9.7.3 | ANALYSIS AND OPTIMIZATION OF VARIABLE-LATENCY DESIGNS IN THE PRESENCE OF TIMING VARIABILITY Speaker: Kai-Chiang Wu, Department of Computer Science, National Chiao Tung University, Hsinchu, Taiwan, TW Authors: Chang-Lin Tsai, Chao-Wei Cheng, Ning-Chi Huang and Kai-Chiang Wu, National Chiao Tung University, TW Abstract Circuit performance has been the key design constraint for over a decade. Variable-latency design (VLD) paradigm was proposed for optimizing the overall performance in terms of throughput. In addition, process variations and aging effects manifest themselves as gate delay shifts, and in turn cause variability of circuit timing (timing variability). Required for dealing with the impact of timing variability better, detailed evaluation and analysis of circuit timing for VLD are actually not straightforward. In this paper, we present a systematic methodology for analyzing a VLD circuit, and identifying critical 1-cycle and 2-cycle paths/gates. Based on the criticality analysis, a gate sizing framework using particle swarm optimization (PSO) is proposed. Our objective is, in a less pessimistic fashion, making constructed VLD circuits better (less vulnerable to timing variability). The proposed framework is experimentally verified to be runtime-efficient and able to provide promising results. On average, an extra timing margin of 11% can be obtained without lengthening the clock period, and only 4% area overhead is introduced. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 10:00 | IP4-17, 345 | CANDY-TM: COMPARATIVE ANALYSIS OF DYNAMIC THERMAL MANAGEMENT IN MANY-CORES USING MODEL CHECKING Speaker: Muhammad Shafique, Institute of Computer Engineering, Vienna University of Technology (TU Wien), AT Authors: Syed Ali Asadullah Bukhari1, Faiq Khalid Lodhi2, Osman Hasan2, Muhammad Shafique3 and Joerg Henkel4 1National University of Sciences and Technology - School of Electrical Engineering and Computer Science, PK; 2School of Electrical Engineering and Computer Science National University of Sciences and Technology (NUST), PK; 3Vienna University of Technology (TU Wien), AT; 4Karlsruhe Institute of Technology, DE Abstract Dynamic thermal management (DTM) techniques based on task migration provide a promising solution to mitigate thermal emergencies and thereby ensuring safe operation and reliability of Many-Core systems. These techniques can be classified as central or distributed on the basis of a central DTM controller for the whole system or individual DTM controllers for each core or set of cores in the system, respectively. However, having a trustworthy comparison between central (c-) and distributed (d-) DTM techniques to find out the most suitable one for a given system is quite challenging. This is primarily due to the systemic difference between cDTM and dDTM controllers, and the inherent non-exhaustiveness of simulation and emulation methods conventionally used for DTM analysis. In this paper, we present a novel methodology called CAnDy-TM (stands for Comparative Analysis of Dynamic Thermal Management) that employs Model Checking to perform formal comparative analysis for cDTM and dDTM techniques. We identify a set of generic functional and performance properties to provide a common ground for their comparison. We demonstrate the usability and benefits of our methodology by comparing state-of-the-art cDTM and dDTM techniques, and illustrate which technique is good w.r.t. thermal stability and other task migration parameters. Such an analysis helps in selecting the most appropriate DTM for a given chip. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 10:01 | IP4-18, 57 | POWER PRE-CHARACTERIZED MESHING ALGORITHM FOR FINITE ELEMENT THERMAL ANALYSIS OF INTEGRATED CIRCUITS Speaker: Shohdy Abdelkader, Software Developer, EG Authors: Shohdy Abdelkader1, Alaa ElRouby2 and Mohamed Dessouky1 1Mentor, EG; 2Electric and Electronic Department, Faculty of Engineering and Natural Science, Yildirim Beyazit University, TR Abstract In this paper we present an adaptive meshing technique suitable for steady state finite element (FE) based thermal analysis of integrated circuits (ICs). The algorithm presented is a non iterative one where the technology used is first pre-characterized. The characterization results are then used for scanning the layout to detect high power regions then fine meshing them. Finally, the analysis is done only once. This makes it faster than conventional iterative adaptive meshing methods. The algorithm results showed comparable accuracy and better performance when compared to the flux based (iterative) and the power aware (non iterative) algorithms. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 10:00 | End of session Coffee Break in Exhibition Area On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area. Tuesday, March 28, 2017
Wednesday, March 29, 2017
Thursday, March 30, 2017
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