Date: Tuesday 28 March 2017
Time: 14:30 - 16:00
Location / Room: 4BC
Organisers:
Xiaobo Sharon Hu, University of Notre Dame, US
Michael Niemier, University of Notre Dame, US
Chair:
Xiaobo Sharon Hu, University of Notre Dame, US
Co-Chair:
Pierre-Emmanuel Gaillardon, The University of Utah at Salt Lake City, US
There is ever-growing interest in alternative computational models (e.g., neural networks, etc.), as well as how emerging technologies can best be exploited to address application-level needs. This hot topic session addresses the above issues from the perspective of benchmarking. It considers the impact of emerging devices, circuits, and architectures at the application level in the context of new metrics and benchmarking methodologies being developed via the Semiconductor Research Corporation (SRC). Subsequent presentations highlight benchmarking and design space exploration efforts that consider application-level energy and performance in the context of computational accuracy. They also highlight infrastructure that can be used to compare different devices, circuits, and architectures that ultimately address the same information processing task.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 14:30 | 3.2.1 | BEYOND-CMOS NON-BOOLEAN LOGIC BENCHMARKING: INSIGHTS AND FUTURE DIRECTIONS Speaker: Azad Naeemi, Georgia Institute of Technology, US Authors: Chenyun Pan and Azad Naeemi, Georgia Institute of Technology, US Abstract Emerging technologies are facing significant challenges to compete with CMOS with respect to Boolean logic. There is an increasing need for using non-traditional circuits to realize the full potential of beyond-CMOS devices. This paper presents a uniform benchmarking methodology for non-Boolean computation based on the cellular neural network (CNN) for a variety of beyond-CMOS device technologies, including charge- based and spintronic devices. Three types of CNN implementations are benchmarked for a given input noise and recall accuracy target using analog, digital, and spintronic circuits. Results demonstrate that spintronic devices are promising candidates to implement CNNs, where up to 3× EDP improvement is predicted in domain wall devices compared to its conventional CMOS counterpart. This shows that alternative non-Boolean computing platforms are crucial for developing future emerging technologies. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 15:00 | 3.2.2 | UNDERSTANDING THE DESIGN OF IBM NEUROSYNAPTIC SYSTEM AND ITS TRADEOFFS: A USER PERSPECTIVE Speaker: Yiran Chen, Duke University, US Authors: Hsin-Pai Cheng, Wei Wen, Chunpeng Wu, Sicheng Li, Hai (Helen) Li and Yiran Chen, University of Pittsburgh, US Abstract As a large-scale commercial spiking-based neuromorphic computing platform, IBM TrueNorth processor received tremendous attentions in society. However, one of the known issues in TrueNorth design is the limited precision of synaptic weights. The current workaround is running multiple neural network copies in which the average value of each synaptic weight is close to that in the original network. We theoretically analyze the impacts of low data precision in the TrueNorth chip on inference accuracy, core occupation, and performance, and present a probability-biased learning method to enhance the inference accuracy through reducing the random var-iance of each computation copy. Our experimental results proved that the proposed techniques considerably improve the computa-tion accuracy of TrueNorth platform and reduce the incurred hard-ware and performance overheads. Among all the tested methods, L1TEA regularization achieved the best result, say, up to 2.74% accuracy enhancement when deploying MNIST application onto TrueNorth platform. In May 2016, IBM TrueNorth team imple-mented convolutional neural networks (CNN) on TrueNorth pro-cessor and coincidently use a similar method, say, trinary weights, {-1, 0, 1}. It achieves near state-of-the-art accuracy on 8 standard datasets. In addition, to further evaluate TrueNorth performance on CNN, we test similar deep convolutional networks on True North, GPU and FPGA. Among all, GPU has the highest through-put. But if we consider energy consumption, TrueNorth processor is the most energy efficient one, say, > 6000 frames/sec/Watt. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 15:30 | 3.2.3 | CELLULAR NEURAL NETWORK FRIENDLY CONVOLUTIONAL NEURAL NETWORKS - CNNS WITH CNNS Speaker: Michael Niemier, University of Notre Dame, US Authors: András Horváth1, Michael Hillmer2, Qiuwen Lou2, X, Sharon Hu2 and Michael Niemier2 1Pázmány Péter Catholic University, HU; 2University of Notre Dame, US Abstract This paper will discuss the development and evaluation of a cellular neural network (CeNN)-friendly deep learning network that addresses the MNIST digit recognition problem. Prior work has shown that CeNNs leveraging emerging technologies such as tunnel transistors can improve energy or EDP of CeNNs, while simultaneously offering richer/more complex functionality. Important questions to address are what applications can benefit from CeNNs, and whether CeNNs can eventually outperform other alternatives at the application-level in terms of energy, performance, and accuracy. This paper begins to address these questions by using the MNIST problem as a case study. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 16:00 | End of session Coffee Break in Exhibition Area On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area. Tuesday, March 28, 2017
Wednesday, March 29, 2017
Thursday, March 30, 2017
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