Date: Thursday 30 March 2017
Time: 16:00 - 17:30
Location / Room: 3C
Chair:
Pascal Vivet, CEA-Leti, FR
Co-Chair:
Hiroshi Nakamura, University of Tokyo, JP
This session covers a wide scope on power modeling and estimation in circuit design. The first paper presents a new model for modeling electromigration in power grid network, taking into account transient effects. The second paper introduces a fast and accurate thermal simulator for 3D circuits, taking into acccount thermal leakage dependency. The third paper proposes a new identification technique of fine grain power sources for multi-core without the knowledge of the thermal model. The last paper presents rule based checking for quick verification at implementation level of the power intent defined in UPF.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 16:00 | 12.5.1 | PHYSICS-BASED ELECTROMIGRATION MODELING AND ASSESSMENT FOR MULTI-SEGMENT INTERCONNECTS IN POWER GRID NETWORKS Speaker: Xiaoyi Wang, Beijing University of Technology, CN Authors: Xiaoyi Wang1, Hongyu Wang2, Jian He1, Sheldon X.-D. Tan3, Yici Cai4 and Shengqi Yang2 1Beijing Advanced Innovation Center for Future Internet Technology, Beijing Engineering Research Center for IoT Software and Systems, Beijing University of Technology, CN; 2Beijing University of Technology, CN; 3University of California, Riverside, US; 4TsingHua University, CN Abstract Electromigration (EM) is considered to be one of the most important reliability issues for current and future ICs in 10nm technology and below. In this paper we focus on the EM stress evaluation for one-dimensional multi-segment interconnect wires in which all the segments have the same direction, which is a common routing structure for power grid networks. The proposed method, which is based on integral transform technique, could efficiently calculate the hydrostatic stress evolution for multi-segment metal wires stressed with different current densities. The new method can also naturally consider the pre-existing residual stresses coming from thermal or other stress sources. Based on this new transient EM assessment method, a full-chip assessment algorithm for power grid networks is then proposed. The new algorithm is also based on the IR-drop metrics for failure assessment of the power grid networks. However, it finds the precise location and time of EM-induced void nucleation by directly checking the time-changing hydrostatic stresses of all the wires. The resulting EM assessment method can ensure sufficient accuracy of the EM verification for large scale power grid networks without sacrificing the efficiency. The accuracy of the proposed transient analysis approach is validated against the numerical analysis. Also the resulting EM-aware full-chip power grid reliability analysis has been demonstrated and compared with existing methods. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 16:30 | 12.5.2 | A FAST LEAKAGE AWARE THERMAL SIMULATOR FOR 3D CHIPS Speaker: Hameedah Sultan, IIT Delhi, IN Authors: Hameedah Sultan and Smruti R. Sarangi, IIT Delhi, IN Abstract In this paper, we propose, 3DSim, which is an ultrafast thermal simulator for 3D chips. It simulates the effects of both dynamic and leakage power. Our technique captures the steady state as well as the transient response with a high speed and good accuracy. 3DSim uses an approach based on Green's functions, where a Green's function is defined as the impulse response of a unit power source. Our approach incorporates the effects of the leakage-temperature feedback loop, exploits the radial symmetry in the thermal profile, and uses Hankel transforms to yield a closed form solution for the leakage aware Green's function. To further speed up our technique, we use fast numerical discrete Hankel transforms, and pre-compute and store certain functions in a lookup table. Our approach fundamentally converts a 3D problem to a set of 1D problems, thus leading to a 68X speedup as compared to competing simulators with an error limited to 1.5C. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 17:00 | 12.5.3 | BLIND IDENTIFICATION OF POWER SOURCES IN PROCESSORS Speaker: Sherief Reda, Brown University, US Authors: Sherief Reda1 and Adel Belouchrani2 1Brown University, US; 2ENP, Algeria, DZ Abstract The ability to measure power consumption is at the heart of power and thermal management techniques. Modern processors are equipped with hardware monitoring mechanisms that can measure total power. However, this lumped measurement is not sufficient if there is a need to execute fine-grain thermal and power management techniques. This paper proposes a new direction for identifying the fine-grain sources of power consumption in many-core processors. For the first time, we show that it is possible to simultaneously identify both the power consumption of different cores and the thermal model of the chip from just the measurements of the thermal sensors and the total power consumption measurement. Our identification technique is blind as it does not require design knowledge of the thermal model to identify the power sources. Furthermore, our technique makes no use of the performance counters, which reduces its overhead, and works seamlessly with dynamic voltage and frequency scaling. We implement our technique on a real multi-core CPU-GPU processor-based system, and we show the ability to identify the runtime power consumption of the individual cores using just the total power measurement and the measurements of the thermal sensors under different workloads. We also verify the superior accuracy of our approach using results from a controlled simulation environment. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 17:15 | 12.5.4 | FAST LOW POWER RULE CHECKING FOR MULTIPLE POWER DOMAIN DESIGN Speaker: Iris Hui-Ru Jiang, National Chiao Tung University, TW Authors: Chien-Pang Lu1 and Iris Hui-Ru Jiang2 1MediaTek, TW; 2National Chiao Tung University, TW Abstract Power management via multiple power domains can effectively save power by dynamically turning off idle domains. To control domains of a design, introducing low power intent complicates the physical implementation and verification process. During the physical implementation stage, the optimization or manual ECO could be tedious, and error-prone on power/ground signal connections. Therefore, in this paper, we focus on low power rule checking at the physical implementation stage for multiple power domain design. Existing methods adopt an iterative approach, which identifies one error at a time, thus possibly requiring multiple iterations. Different from them, we propose a fast low power rule checking approach to detect all errors at one time. To do so, we separate all paths into inner-domain and cross-domain paths and extract cross-domain net topology before power rule verification. Based on the global topology, we can verify the correctness of connections and detect all errors at the same time. Experimental results show the effectiveness and efficiency of our approach, achieving 3.62X speedups to detect all errors compared with the iterative approach. Moreover, our approach can identify complicated bugs to facilitate subsequent bug fixing. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 17:30 | End of session | |