Date: Thursday 30 March 2017
Time: 14:00 - 15:30
Location / Room: 5A
Chair:
Maksim Jenihhin, Tallinn University f Technology, EE
Co-Chair:
Antonio Miele, Politecnico di Milano, IT
The section presents two papers investigating the effects of soft errors on critical registers and hardware methods to detect intrusion attacks in microprocessors. A third paper provides a solution for estimating multiprocessor expected lifetime.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 14:00 | 11.6.1 | CHARACTERIZATION OF STACK BEHAVIOR UNDER SOFT ERRORS Speaker: Junchi Ma, School of Computer Science and Engineering, Southeast University, CN Authors: Junchi Ma and Yun Wang, School of Computer Science and Engineering, Southeast University, CN Abstract As process technology scales, electronic devices become more susceptible to soft error induced by radiation. The stack in the memory implements procedure calls and its behavior under soft error has not been studied yet. To analyze the effects of soft error on the stack behavior, we conduct a series of fault injection experiment in the IA-32 instruction set architecture. The injection targets are the ESP register (used as the stack pointer) and the EBP register (used as the stack-frame base pointer). We obtain a few important observations from the fault injection experiment. Results show that injections on ESP lead to silent data corruption (SDC) or benign only if the flipped ESP points to another return address when executing the RET instruction, otherwise most of the injections cause crash. The injected bits of these SDC and benign cases are distributed in the particular bits (4-7) and the reason for the distribution is given. Moreover, flipped EBP may cause a series of infinite return operations, which is defined as return cycle. We describe the basic mechanism of return cycle and the essential condition for its occurrence. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 14:30 | 11.6.2 | MULTI-ARMED BANDITS FOR EFFICIENT LIFETIME ESTIMATION IN MPSOC DESIGN Speaker: Brett Meyer, McGill University, CA Authors: Calvin Ma, Aditya Mahajan and Brett Meyer, McGill University, CA Abstract Reliability in integrated circuits is becoming a critical issue with the miniaturization of electronics. Smaller process technologies have led to higher power densities, resulting in higher temperatures and earlier device wear-out. One way to mitigate failure is by over-provisioning resources and remapping tasks from failed components to components with spare capacity, or slack. Since the slack allocation design space is large, finding the optimal is difficult, as brute-force approaches are impractical. During design space exploration, device lifetimes are typically evaluated using Monte-Carlo Simulation (MCS) by sampling each design equally; this method is inefficient since poor designs are evaluated as accurately as good designs. A better method will focus sampling time on the designs that are difficult to distinguish, reducing the time required to evaluate a set of designs; this can be accomplished using Multi-armed Bandit (MAB) Algorithms. This work demonstrates that MAB achieve the same level of accuracy as MCS in 1.45 to 5.26 times fewer samples. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 15:00 | 11.6.3 | HARDWARE-BASED ON-LINE INTRUSION DETECTION VIA SYSTEM CALL ROUTINE FINGERPRINTING Speaker: Yiorgos Makris, The University of Texas at Dallas, US Authors: Liwei Zhou and Yiorgos Makris, The University of Texas at Dallas, US Abstract We introduce a hardware-based methodology for performing on-line intrusion detection in microprocessors. The proposed method extracts fingerprints from the basic blocks of the routine executed in response to a system call and examines their validity using a Bloom filter. Implementation in hardware renders spoofing attacks, to which operating system or hypervisor-level intrusion detection methods are vulnerable, ineffective. The proposed method is evaluated using kernel rootkits which covertly modify the system call service routines of a Linux operating system running on a 32-bit x86 architecture, implemented in the Simics simulation environment, while hardware overhead is evaluated using a predictive 45nm PDK. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 15:30 | IP5-16, 935 | EVALUATING MATRIX REPRESENTATIONS FOR ERROR-TOLERANT COMPUTING Speaker: Pareesa Golnari, Princeton University, US Authors: Pareesa Ameneh Golnari and Sharad Malik, Princeton University, US Abstract We propose a methodology to determine the suitability of different data representations in terms of their error-tolerance for a given application with accelerator-based computing. This methodology helps match the characteristics of a representation to the data access patterns in an application. For this, we first identify a benchmark of key kernels from linear algebra that can be used to construct applications of interest using any of several widely used data representations. This is then used in an experimental framework for studying the error tolerance of a specific data format for an application. As case studies, we evaluate the error-tolerance of seven data-formats on sparse matrix to vector multiplication, diagonal add, and two machine learning applications i) principal component analysis (PCA), which is a statistical technique widely used in data analysis and ii) movie recommendation system with Restricted Boltzmann Machine (RBM) as the core. We observe that the Dense format behaves well for complicated data accesses such as diagonal accessing but is poor in utilizing local memory. Sparse formats with simpler addressing methods and a careful selection of stored information, e.g., CRS and ELLPACK, demonstrate a better error-tolerance for most of our target applications. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 15:31 | IP5-17, 131 | SIMULATION-BASED DESIGN PROCEDURE FOR SUB 1 V CMOS CURRENT REFERENCE Speaker: Dmitry Osipov, University of Bremen, DE Authors: Dmitry Osipov and Steffen Paul, University of Bremen, DE Abstract This paper presents a new compact current reference and a simulation-based design procedure to establish the circuit parameters quicly and efficiently. To verify the proposed design procedure, two sub 1~V example circuits for two different reference current values (80 nA and 800 nA) were designed and simulated using 0.35 µm CMOS technology. The circuits are robust against supply voltage variation without the need for external bandgap. A line sensitivity of approximately 1-2%/V over the supply voltage range from sub 1 V is achieved in both cases. The simulated temperature coefficient (TC) values are 93 ppm/°C and 197 ppm/°C in the temperature range from 0°C to 120°C for the 800 nA and 80 nA references, respectively. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 15:30 | End of session Coffee Break in Exhibition Area On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area. Tuesday, March 28, 2017
Wednesday, March 29, 2017
Thursday, March 30, 2017
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