Date: Thursday 30 March 2017
Time: 14:00 - 15:30
Location / Room: 4BC
Chair:
Weisheng Zhao, Beihang University, CN
Co-Chair:
Jean-Michel Portal, Aix-Marseille Université, FR
Memory design based on emerging technologies is critical for the future VLSI design targeting low power and high performance. This session involves novel design method and evaluation tool for emerging technologies (i.e. STT-MRAM, Racetrack memory, Phase Change Memory and Ferroelectric memory etc.) including variation aware design, novel architecture implementation and reliability concern.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 14:00 | 11.2.1 | (Best Paper Award Candidate) HYBRID VC-MTJ/CMOS NON-VOLATILE STOCHASTIC LOGIC FOR EFFICIENT COMPUTING Speaker: Shaodi Wang, University of California, Los Angeles, US Authors: Shaodi Wang1, Saptadeep Pal1, Tianmu Li2, Andrew Pan2, Cecile Grezes2, Pedram Khalili-Amiri2, Kang L. Wang2 and Puneet Gupta2 1University of California, Los Angeles, US; 2UCLA, US Abstract In this paper, we propose a non-volatile stochastic computing (SC) scheme using voltage-controlled magnetic tunnel junction (VC-MTJ) and negative differential resistance (NDR). The proposed design includes a VC-MTJ based true stochastic bit stream generator and VC-MTJ and NDR based stochastic adder, multiplier, register, which are experimentally demonstrated using 60nm VC-MTJ and CMOS NDR connected on die. These components are then used to realize FIR filter and AdaBoost (machine-learning algorithm). 3X - 37X energy advantage is shown for the proposed SC compared with CMOS binary arithmetic ASIC and SC designs. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 14:30 | 11.2.2 | DESIGN AND BENCHMARKING OF FERROELECTRIC FET BASED TCAM Speaker: Xunzhao Yin, University of Notre Dame, US Authors: Xunzhao Yin, Michael Niemier and X. Sharon Hu, University of Notre Dame, US Abstract We consider how emerging transistor technologies, specifically ferroelectric field effect transistors (or FeFETs), can realize compact and energy efficient ternary content addressable memories (TCAMs). As Moore's Law-based performance scaling trends slow, and many computational tasks of interest are now more data-centric than compute-centric, researchers are looking to improve performance/save energy by integrating efficient and compact logic/processing elements into various levels of the memory hierarchy. Potential benefits include reduced I/O traffic, energy/delay from data transfers, etc. A TCAM is an example of a logic-in-memory element that is ubiquitous in routers, caches, databases, and even neural networks. Not surprisingly, researchers continue to study how emerging technologies could lead to improved TCAMs. Recent work has considered how non-volatile (NV) memory technologies (e.g., resistive random access memory (ReRAM) or magnetic tunnel junctions (MTJs)) could best be used to construct low energy, NV TCAMs. However, acceptable Ron-Roff ratios and the two terminal nature of these devices introduce energy and area overheads. Due to hysteresis in a device's I-V curve, an FeFET-based NV TCAM, offers low area overhead, as well as search energies and search speeds that are superior to other TCAM designs (i.e., based on MTJ, ReRAM and CMOS in array- and architectural-level evaluations.) Download Paper (PDF; Only available from the DATE venue WiFi) |
| 15:00 | 11.2.3 | LEVERAGING ACCESS PORT POSITIONS TO ACCELERATE PAGE TABLE WALK IN DWM MAIN MEMORY Speaker: Chengmo Yang, University of Delaware, US Authors: Hoda Aghaei Khouzani1, Pouya Fotouhi2, Chengmo Yang1 and Guang R. Gao2 1University of Delaware, US; 2Department of Electrical and Computer Engineering, University of Delaware, US Abstract Domain Wall Memory (DWM) with ultra-high density and comparable read/write latency to SRAM/DRAM is an attractive replacement for CMOS-based devices. Unlike SRAM/DRAM, DWM has non-uniform data access latency that is proportional to the number of shift operations. While previous works have demonstrated the feasibility of using DWM as main memory and have proposed different ways to alleviate the impact of shift operations, none of them have addressed the performance-critical metadata accesses, in particular page table accesses. To bridge this gap, this paper aims at accelerating page table walk in DWM main memory from two innovative aspects. First of all, we propose a new page table layout and leverage the positions of access ports in DWM to differentiate the state of page table entries. In addition, we propose a technique to pre-align the access ports to the positions to be accessed in the near future, thus hiding shift latency to the maximum extent. Since both address translation and context switching are affected by page table access latency, the proposed technique can effectively improve system performance and user experience. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 15:15 | 11.2.4 | VAET-STT: A VARIATION AWARE ESTIMATOR TOOL FOR STT-MRAM BASED MEMORIES Speaker: Sarath Mohanachandran Nair, KIT, Germany, DE Authors: Sarath Mohanachandran Nair1, Rajendra Bishnoi2, Mohammad Saber Golanbari1, Fabian Oboril1 and Mehdi Tahoori1 1Karlsruhe Institute of Technology, DE; 2Karlsruhe Institiute of Technology, DE Abstract Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a promising candidate to replace CMOS based on-chip memories due to its advantages such as non-volatility, high density and scalability. However, its stochastic switching and higher sensitivity to process variation compared to CMOS memories can significantly affect its performance, energy and reliability. Although a few works exist which analyze the impact of process variation at the bit-cell level, such analysis at the system level is missing. We have bridged this gap in our work. Specifically, we quantify the effect of stochasticity and process variations from the cell-level to the overall memory system and perform a variation-aware memory configuration optimization for energy or performance while meeting reliability constraints. Our system-level variation-aware framework has been built on top of the well-known NVSim engine. The results show that our framework can provide more realistic margins and the optimized variation-aware memory configuration could be significantly different from the conventional framework. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 15:30 | IP5-7, 52 | PROTECT NON-VOLATILE MEMORY FROM WEAR-OUT ATTACK BASED ON TIMING DIFFERENCE OF ROW BUFFER HIT/MISS Speaker: Haiyu Mao, Tsinghua University, CN Authors: Haiyu Mao1, Xian Zhang2, Guangyu Sun2 and Jiwu Shu1 1Tsinghua University, CN; 2Peking University, CN Abstract Non-volatile Memories(NVMs), such as PCM and ReRAM, have been widely proposed for future main memory design because of their low standby power, high storage density, fast access speed. However, these NVMs suffer from the write endurance problem. In order to prevent a malicious program from wearing out NVMs deliberately, researchers have proposed various wear-leveling methods, which remap logical addresses to physical addresses randomly and dynamically. However, we discover that side channel leakage based on NVM row buffer hit information can reveal details of address remappings. Consequently, it can be leveraged to side-step the wear-leveling. Our simulation shows that the proposed attack method in this paper can wear out a NVM within 137 seconds, even with the protection of state-of-the-art wear-leveling schemes. To counteract this attack, we further introduce an effective countermeasure named Intra-Row Swap(IRS) to hide the wear-leveling details. The basic idea is to enable an additional intra-row block swap when a new logical address is remapped to the memory row. Experiments demonstrate that IRS can secure NVMs with negligible timing/energy overhead, compared with previous works. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 15:32 | IP5-8, 622 | EFFECTS OF CELL SHAPES ON THE ROUTABILITY OF DIGITAL MICROFLUIDIC BIOCHIPS Speaker: Oliver Keszöcze, University of Bremen, DE Authors: Kevin Leonard Schneider1, Oliver Keszocze1, Jannis Stoppe1 and Rolf Drechsler2 1University of Bremen, DE; 2University of Bremen/DFKI GmbH, DE Abstract Digital microfluidic biochips (DMFBs) are an emerging technology promising a high degree of automation in laboratory procedures by means of manipulating small discretized amounts of fluids. A crucial part in conducting experiments on biochips is the routing of discretized droplets. While doing so, droplets must not enter each others' interference region to avoid unintended mixing. This leads to cells in the proximity of the droplet being impassable for others. For different cell shapes, the effect of these temporary blockages varies as the adjacency of cells changes with their shapes. Yet, no evaluation with respect to routability in relation to cell shapes has been conducted so far. This paper analyses and compares various tessellations for the field of cells. Routing benchmarks are mapped to these and the results are compared in order to determine if and how cell shapes affect the performance of DMFBs, showing that certain cell shapes are superior to others. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 15:30 | End of session Coffee Break in Exhibition Area On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area. Tuesday, March 28, 2017
Wednesday, March 29, 2017
Thursday, March 30, 2017
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