W01 TRUDEVICE 2016: Workshop on Trustworthy Manufacturing and Utilization of Secure Devices

Agenda

Time	Label	Session
08:30	W01.1	Opening Session
08:30	W01.1.1	TRUDEVICE: Trustworthy Manufacturing and Utilization of Secure Devices Giorgio Di Natale¹, Ilia Polian², Francesco Regazzoni³ and Nicolas Sklavos⁴ ¹LIRMM, FR; ²University of Passau, DE; ³AlaRI, CH; ⁴University of Patras, GR
08:45	W01.2	Keynote Talk 1 Chair: Ilia Polian, University of Passau, DE
08:45	W01.2.1	On the need for side-channel protection for IoT devices De Mulder Elke, Cryptography Research, Rambus, FR
09:30	W01.3	Session 1 Chair: Tim Güneysu, University of Bremen, DE
09:30	W01.3.1	Assessment of the laser-induced fault model towards continuous CMOS technology shrinkage. Jean-Max Dutertre¹, Philippe Candelier², Clement Champeix³, Stephan De Castro⁴, Giorgio Di Natale⁴, Marie-Lise Flottes⁴, Marc Lacruche¹, Mathieu Lisart², Jean-Baptiste Rigaud¹, Cyril Roscian⁵, Bruno Rouzeyre⁶ and Alexandre Sarafianos⁷ ¹ENSM-SE, FR; ²STMicroelectronics,, FR; ³STMicroelectronics, FR; ⁴LIRMM, FR; ⁵École Nationale Supérieure des Mines de Saint-Étienne, FR; ⁶University Montpellier, FR; ⁷ST Microelectronics,, FR
09:45	W01.3.2	Relaibility Model of TMR System Considering Transient Faults Martin Danhel¹, Filip Štepanek² and Hana Kubatova¹ ¹Faculty of Information Technology - Czech Technical University in Prague, CZ; ²-, CZ
10:00	W01.3.3	Scan Chain Encryption for the Test, Diagnosis and Debug of Secure Circuits Giorgio Di Natale¹, Marie-Lise Flottes¹, Bruno Rouzeyre², Paolo PRINETTO³ and Marco Restifo³ ¹LIRMM, FR; ²University Montpellier, FR; ³Politecnico di Torino, IT
10:15	W01.3.4	Evolutionary Algorithms and the Design of S-boxes for Energy Efficient Ciphers Stjepan Picek¹, Bohan Yang², Vladimir Rožić³, Nele Mentens⁴ and Ingrid Verbauwhede⁵ ¹Faculty of Electrical Engineering and Computing, HR; ²ESAT/COSIC, BE; ³K.U.Leuven, BE; ⁴ESAT/COSIC and iMinds, KU Leuven, BE; ⁵KU Leuven and UCLA, BE
10:30	W01.4	Poster Session 1 Chair: Nicolas Sklavos, University of Patras, GR
10:30	W01.4.1	Relaibility Model of TMR System Considering Transient Faults Martin Danhel¹, Filip Štepanek² and Hana Kubatova¹ ¹Faculty of Information Technology - Czech Technical University in Prague, CZ; ²-, CZ
10:30	W01.4.2	A 16-bit FPGA processor for π -Cipher Mohamed El-Hadedy¹, Hristina Mihajloska², Danilo Gligoroski³ and Kevin Skadron⁴ ¹Research Associate, US; ²University Ss Cyril and Methodius, MK; ³NTNU, NO; ⁴University of Virginia, US
10:30	W01.4.3	AndTrojanID? Android Trojans Identification Using Dynamic Feature Jelena Milosevic¹, Alberto Ferrante² and Miroslaw Malek² ¹ALaRI, CH; ²ALaRI - USI, CH
10:30	W01.4.4	Cyber Attack/Defense Algorithms Based on Data Hiding in Compressed Video Stream Yaron Amsalem and Ofer Hadar, Ben-Gurion University, IL
10:30	W01.4.5	STT-MTJ-Based True Random Number Generator Elena Ioana Vatajelu¹, Giorgio Di Natale² and Paolo PRINETTO³ ¹POLITO, IT; ²LIRMM, FR; ³Politecnico di Torino, IT
10:30	W01.4.6	Characterization of high-speed Q-RNG using CMOS photon counting detectors Emna Amri¹, Samuel Burri², Yacine Felk¹, Francesco Regazzoni³, Damien Stucki¹, Siddharth Sinha⁴, Edoardo Charbon⁵ and Hugo Zbinden⁶ ¹IDQuantique, CH; ²EPFL, CH; ³AlaRI, CH; ⁴TUDelft, NL; ⁵TUDelft and EPFL, CH; ⁶Université de Genève, CH
10:30	W01.4.7	Study of Security-Awareness in Cyber-Physical Internet of Things Viacheslav Izosimov¹ and Martin Törngren² ¹The Royal Institute of Technology (KTH), SE; ²KTH Royal Institute of Technology, SE
10:30	W01.4.8	Assessment of the laser-induced fault model towards continuous CMOS technology shrinkage Jean-Max Dutertre¹, Philippe Candelier², Clement Champeix³, Stephan De Castro⁴, Giorgio Di Natale⁴, Marie-Lise Flottes⁴, Marc Lacruche¹, Mathieu Lisart², Jean-Baptiste Rigaud¹, Cyril Roscian⁵, Bruno Rouzeyre⁶ and Alexandre Sarafianos⁷ ¹ENSM-SE, FR; ²STMicroelectronics,, FR; ³STMicroelectronics, FR; ⁴LIRMM, FR; ⁵École Nationale Supérieure des Mines de Saint-Étienne, FR; ⁶University Montpellier, FR; ⁷ST Microelectronics,, FR
10:30	W01.4.9	Protecting FPGA targets in hostile environment: A proposition for kill-switch in FPGA Debapriya Basu Roy¹, Shivam Bhasin², Jean-Luc Danger², Debdeep Mukhopadhyay³ and Sylvain Guilley² ¹Department of Computer Science and Engineering, Indian Institute of Technology Kharagpur, IN; ²Télécom ParisTech, FR; ³Indian Institute of Technology, IN
11:00	W01.5	Session 2 Chair: Stjepan Picek, Faculty of Electrical Engineering and Computing, HR
11:00	W01.5.1	Utilizing Intrinsic Delay Variability in Complex Digital Circuits for Defining PUF Behavior Matthias Sauer¹, Linus Feiten¹, Bernd Becker¹, Ulrich Rührmair² and Ilia Polian³ ¹University of Freiburg, DE; ²Technische Universität München, DE; ³University of Passau, DE
11:15	W01.5.2	Key reconciliation protocol application to error correction in silicon PUF responses Brice Colombier¹, Bossuet Lilian¹ and David Hely² ¹University of St. Etienne, FR; ²Univ. Grenoble Alpes, FR
11:30	W01.5.3	On metrics to quantify the inter-device uniqueness of Physically Unclonable Functions Linus Feiten, Matthias Sauer and Bernd Becker, University of Freiburg, DE
11:45	W01.5.4	TOTAL: TRNG On-the-fly Testing for Attack detection using Lightweight hardware Bohan Yang¹, Vladimir Rožić², Nele Mentens³, Wim Dehaene⁴ and Ingrid Verbauwhede⁵ ¹ESAT/COSIC, BE; ²K.U.Leuven, BE; ³ESAT/COSIC and iMinds, KU Leuven, BE; ⁴imec vzw, KU Leuven, BE; ⁵KU Leuven and UCLA, BE
12:00	W01.5.5	STT-MTJ-Based True Random Number Generator Elena Ioana Vatajelu¹, Giorgio Di Natale² and Paolo PRINETTO³ ¹POLITO, IT; ²LIRMM, FR; ³Politecnico di Torino, IT
13:00	W01.6	Keynote Talk 2 Chair: Giorgio Di Natale, LIRMM, FR
13:00	W01.6.1	Implant security: The new deep end Christos Strydis, Erasmus Medical Center, NL
13:45	W01.7	Session 3 Chair: Nele Mentens, ESAT/COSIC and iMinds, KU Leuven, BE
13:45	W01.7.1	Malicious hardware logic detection based on combinatorial testing Paris Kitsos¹, Dimitris Simos², Kyriakos Stefanidis³ and Artemios G. Voyiatzis² ¹Technological Educational Institute of Western Greece, GR; ²SBA Research, AT; ³ISI/Athena RC, GR
14:00	W01.7.2	Duplication-based Concurrent Detection of Hardware Trojans in Integrated Circuits Palanichamy Manikandan¹, Papa-Sidy Ba², Sophie Dupuis², Marie-Lise Flottes², Giorgio Di Natale² and Bruno Rouzeyre³ ¹LIRMM, Univ. Montpellier, Montpellier, France, FR; ²LIRMM, FR; ³University Montpellier, FR
14:15	W01.7.3	Low-Overhead Hardware Trojan insertion in Cryptographic ICs Ioannis Voyiatzis¹, P. Kyrkos², Thanos Milidonis¹ and Costas Efstathiou¹ ¹Technological Educational Institute of Athens, GR; ²Department of Informatics, Technological Educational Institute of Athens, GR
14:30	W01.8	Poster Session 2 Chair: Nicolas Sklavos, University of Patras, GR
14:30	W01.8.1	Relaibility Model of TMR System Considering Transient Faults Martin Danhel¹, Filip Štepanek² and Hana Kubatova¹ ¹Faculty of Information Technology - Czech Technical University in Prague, CZ; ²-, CZ
14:30	W01.8.2	A 16-bit FPGA processor for π -Cipher Mohamed El-Hadedy¹, Hristina Mihajloska², Danilo Gligoroski³ and Kevin Skadron⁴ ¹Research Associate, US; ²University Ss Cyril and Methodius, MK; ³NTNU, NO; ⁴University of Virginia, US
14:30	W01.8.3	AndTrojanID? Android Trojans Identification Using Dynamic Feature Jelena Milosevic¹, Alberto Ferrante² and Miroslaw Malek² ¹ALaRI, CH; ²ALaRI - USI, CH
14:30	W01.8.4	Cyber Attack/Defense Algorithms Based on Data Hiding in Compressed Video Stream Yaron Amsalem and Ofer Hadar, Ben-Gurion University, IL
14:30	W01.8.5	STT-MTJ-Based True Random Number Generator Elena Ioana Vatajelu¹, Giorgio Di Natale² and Paolo Prinetto³ ¹POLITO, IT; ²LIRMM, FR; ³Politecnico di Torino, IT
14:30	W01.8.6	Characterization of high-speed Q-RNG using CMOS photon counting detectors Emna Amri¹, Samuel Burri², Yacine Felk¹, Francesco Regazzoni³, Damien Stucki¹, Siddharth Sinha⁴, Edoardo Charbon⁵ and Hugo Zbinden⁶ ¹IDQuantique, CH; ²EPFL, CH; ³AlaRI, CH; ⁴TUDelft, NL; ⁵TUDelft and EPFL, CH; ⁶Université de Genève, CH
14:30	W01.8.7	Study of Security-Awareness in Cyber-Physical Internet of Things Viacheslav Izosimov¹ and Martin Törngren² ¹The Royal Institute of Technology (KTH), SE; ²KTH Royal Institute of Technology, SE
14:30	W01.8.8	Assessment of the laser-induced fault model towards continuous CMOS technology shrinkage Jean-Max Dutertre¹, Philippe Candelier², Clement Champeix³, Stephan De Castro⁴, Giorgio Di Natale⁴, Marie-Lise Flottes⁴, Marc Lacruche¹, Mathieu Lisart², Jean-Baptiste Rigaud¹, Cyril Roscian⁵, Bruno Rouzeyre⁶ and Alexandre Sarafianos⁷ ¹ENSM-SE, FR; ²STMicroelectronics,, FR; ³STMicroelectronics, FR; ⁴LIRMM, FR; ⁵École Nationale Supérieure des Mines de Saint-Étienne, FR; ⁶University Montpellier, FR; ⁷ST Microelectronics,, FR
14:30	W01.8.9	Protecting FPGA targets in hostile environment: A proposition for kill-switch in FPGA Debapriya Basu Roy¹, Shivam Bhasin², Jean-Luc Danger², Debdeep Mukhopadhyay³ and Sylvain Guilley² ¹Department of Computer Science and Engineering, Indian Institute of Technology Kharagpur, IN; ²Télécom ParisTech, FR; ³Indian Institute of Technology, IN
15:00	W01.9	Session 4 Chair: Nicolas Sklavos, University of Patras, GR
15:00	W01.9.1	Automatic Side-Channel Leakage Mitigation at the Micro-Architecture Level Hermann Seuschek, Technische Universität München, DE
15:15	W01.9.2	Design and implementation of a waveform-matching based triggering system Arthur Beckers¹, Josep Balasch¹, Benedikt Gierlichs¹ and Ingrid Verbauwhede² ¹Katholieke Universiteit Leuven, BE; ²KU Leuven and UCLA, BE
15:30	W01.9.3	GliFreD: Glitch-Free Duplication Towards Power-Equalized Circuits on FPGAs Alexander Wild¹, Amir Moradi² and Tim Güneysu³ ¹Horst Görtz Institute for IT Security, Ruhr University Bochum, DE; ²Ruhr University Bochum, DE; ³University of Bremen, DE
15:45	W01.10	Session 5
15:45	W01.10.1	Extending Remote Attestation for Hardware Reconfigurable Trusted Platforms Domenico Amelino, Mario Barbareschi, Alessandro Cilardo and Antonino Mazzeo, University of Naples Federico II, IT
16:00	W01.10.2	AndTrojanID? Android Trojans Identification Using Dynamic Feature Jelena Milosevic¹, Alberto Ferrante² and Miroslaw Malek² ¹ALaRI, CH; ²ALaRI - USI, CH
16:15	W01.10.3	Study of Security-Awareness in Cyber-Physical Internet of Things Viacheslav Izosimov¹ and Martin Törngren² ¹The Royal Institute of Technology (KTH), SE; ²KTH Royal Institute of Technology, SE
16:30	W01.10.4	An FPGA Based Third-Party Intellectual Property Isolation Mechanism Mario Barbareschi, Salvatore Miranda and Antonino Mazzeo, University of Naples Federico II, IT
16:45	W01.11	Closing Session
16:45	W01.11.1	Closing Remarks Giorgio Di Natale, LIRMM, FR Ilia Polian¹, Francesco Regazzoni² and Nicolas Sklavos³ ¹University of Passau, DE; ²AlaRI, CH; ³University of Patras, GR