Date: Thursday 17 March 2016
Time: 08:30 - 10:00
Location / Room: Konferenz 6
Chair:
Nader Bagherzadeh, University of California Irvine, US
Co-Chair:
Massoud Daneshtalab, KTH, SE
Multi-core systems-on-chip integrate a growing number of heterogeneous components, leading to increasingly more complex traffic patterns. This section presents three contributions to manage the growing traffic challenges in NoCs: the first paper proposes a traffic splitting model for application-specific NosCs, the second presents a MCAPI-compliant hardware buffer manager to support communication among heterogeneous components, and the third employs an overlay network and scheduling unit to provide latency guarantees for hard real-time transmissions.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 08:30 | 9.2.1 | OLITS: AN OHM'S LAW-LIKE TRAFFIC SPLITTING MODEL BASED ON CONGESTION PREDICTION Speaker: Gaoming Du, Hefei University of Technology, CN Authors: Gaoming Du1, Yanghao Ou1, Xiangyang Li1, Ping Song1, Zhonghai Lu2 and Minglun Gao1 1Hefei University of Technology, CN; 2KTH Royal Institute of Technology, SE Abstract Through traffic splitting, multi-path routing in Network-on-Chip (NoC) outperforms single-path routing in terms of load balance and resource utilization. However, uncontrolled traffic splitting may aggravate network congestion, thus worsen communication delay. We propose OLITS, an Ohm's Law-like traffic splitting model, for application-specific NoC. We first redefine the contention matrix to characterize the flow congestion state, which contains flow parameters such as average flow rate and burstiness. We then define flow resistance as the flow congestion factor extracted from the contention matrix, and use the parallel resistance theory to predicate the congestion state for every target sub-flow. Finally, the traffic splitting proportions of the parallel sub-flows are assigned according to the equivalent flow resistance. Experiments are taken both on 2D and 3D multi-path routing NoCs. The results show that the worst-case delay bound of target flow is significantly improved, and network congestion can be effectively balanced. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 09:00 | 9.2.2 | MCAPI-COMPLIANT HARDWARE BUFFER MANAGER MECHANISM TO SUPPORT COMMUNICATION IN MULTI-CORE ARCHITECTURES Speaker: Romain Lemaire, CEA-Leti, FR Authors: Thiago Raupp da Rosa, Thomas Mesquida, Romain Lemaire and Fabien Clermidy, CEA-Leti, FR Abstract High performance and high power efficiency are two mandatory constraints for multi-core systems in order to successfully handle the most recent applications in several fields, e.g. image processing and communication standards. Nowadays, hardware accelerators are often used along with several processing cores to achieve the desired performance while keeping high power efficiency. However, such systems impose an increased programming complexity due to the lack of software standards that supports heterogeneity, frequently leading to custom solutions. On the other hand, implementing a standard software solution for embedded systems might induce significant overheads. This work presents a hardware mechanism in co-design with a standard programming interface (API) for embedded systems focusing to decrease overheads imposed by software implementation while increasing programmability and communication performance. The results show gains of up to 97% in latency and an increase of 40 times in throughput for synthetic traffics and an average decrease of 95% in communication time for an image processing application. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 09:30 | 9.2.3 | SLACK-BASED RESOURCE ARBITRATION FOR REAL-TIME NETWORKS-ON-CHIP Speaker: Adam Kostrzewa, Technische Universität Braunschweig, DE Authors: Adam Kostrzewa, Selma Saidi and Rolf Ernst, Technische Universität Braunschweig, DE Abstract Networks-on-Chip (NoCs) designed for real-time systems must efficiently deal with a broad diversity of traffic requirements. This demands providing latency guarantees for hard real-time transmissions with minimum impact on performance sensitive best-effort traffic. In this work, we present a novel mechanism which achieves this goal through a slack-based, global and dynamic prioritization of data streams. This is performed using an overlay network and scheduling unit combining local arbitration performed in routers with global scheduling of entire logical transmissions for end to end guarantees. Consequently, our approach allows to decrease both hardware and temporal overhead when compared with existing solutions and to achieve a performance improvement up to 60%. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 10:00 | IP4-7, 180 | PACKET SECURITY WITH PATH SENSITIZATION FOR NOCS Speaker: Travis Boraten, Ohio University, US Authors: Travis Boraten and Avinash Kodi, Ohio University, US Abstract Hardware security is becoming a major concern as integrated circuits (IC) are exponentially growing thanks to technology scaling. With ICs reaching upwards of billions of transistors, detecting hardware trojans (HT) is like finding a needle in a haystack. Therefore, it becomes imperative to protect critical computing infrastructure from malicious attackers attempting to unearth vital information. Security enhancements should offer resiliency to limit their impact on overall chip performance as HTs are likely to slip through detection mechanisms. In this paper, we propose packet-security (P-Sec) a packet validation technique to protect compromised network-on-chip (NoC) architectures from fault injection side channel attacks and covert HT communication by merging two robust error detection schemes, namely algebraic manipulation detection (AMD) and cyclic redundancy check (CRC) codes. With P-Sec, applications containing sensitive and encrypted data can be protected from an ideal attacker using AMD codes at the cost of marginal area and power overhead in the network interface but with enhanced security on demand. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 10:00 | End of session Coffee Break in Exhibition Area |