Date: Wednesday 16 March 2016
Time: 17:00 - 18:30
Location / Room: Konferenz 3
Chair:
Ian O'Connor, Ecole Centrale de Lyon, FR
Co-Chair:
Michael Niemier, University of Notre Dame, US
The first two papers consider hybrid main memories consisting of DRAM and emerging non-volatile memories, and examine system-level optimizations. The last paper considers performance in-memory computing using properties of emerging resistive RAM.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 17:00 | 8.5.1 | AN OPERATING SYSTEM LEVEL DATA MIGRATION SCHEME IN HYBRID DRAM-NVM MEMORY ARCHITECTURE Speaker: Reza Salkhordeh, Sharif University of Technology, IR Authors: Reza Salkhordeh and Hossein Asadi, Sharif University of Technology, IR Abstract With the emergence of Non-Volatile Memories (NVMs) and their shortcomings such as limited endurance and high power consumption in write requests, several studies have suggested hybrid memory architecture employing both Dynamic Random Access Memory (DRAM) and NVM in a memory system. By conducting a comprehensive experiments, we have observed that such studies lack to consider very important aspects of hybrid memories including the effect of: a) data migrations on performance, b) data migrations on power, and c) the granularity of data migration. This paper presents an efficient data migration scheme at the Operating System level in a hybrid DRAM-NVM memory architecture. In the proposed scheme, two Least Recently Used (LRU) queues, one for DRAM section and one for NVM section, are used for the sake of data migration. With careful characterization of the workloads obtained from PARSEC benchmark suite, the proposed scheme prevents unnecessary migrations and only allows migrations which benefits the system in terms of power and performance. The experimental results show that the proposed scheme can reduce the power consumption up to 79% compared to DRAM-only memory and up to 48% compared to the state-of-the art techniques. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 17:30 | 8.5.2 | UNIFIED DRAM AND NVM HYBRID BUFFER CACHE ARCHITECTURE FOR REDUCING JOURNALING OVERHEAD Speaker: Lei Ju, Shandong University, CN Authors: Zhiyong Zhang, Lei Ju and Zhiping Jia, Shandong University, CN Abstract Journaling techniques play an important role in addressing the reliability issue of filesystems caused by the volatile DRAM-based buffer cache. However, journaling techniques introduce a large number of extra storage writes, which greatly degrades the performance of the filesystem. Emerging Non-Volatile Memory (NVM) technologies bring a new perspective of solving the write amplification issue caused by journaling. By adopting NVM as the buffer cache, the committed data can be maintained in NVM before being written back to the storage, thus eliminating the journaling overhead. However, simply replacing DRAM with NVM as the buffer cache suffers from the limited lifetime and relative slow writes of NVM. In this paper, we present a hybrid buffer cache architecture by combing NVM with DRAM to reduce the journaling overhead and overcome the constrains of NVM. In order to better utilize this novel architecture, we first propose a Journaling-Aware Page Management (JAPM) policy. JAPM puts infrequently updated data in NVM to reduce the journaling overhead and frequently updated data in DRAM to improve the write performance and lifetime of the hybrid buffer cache. In addition, data in one transaction may be dispersed in NVM and DRAM simultaneously and different committing policies are required for different storing media, NVM or DRAM. In order to guarantee the atomicity of the transactional execution in the hybrid cache architecture, a Partial In-Place Commit (PIPC) journaling scheme is proposed to coordinate the different committing patterns. We implement the proposed techniques on Linux 3.14.52 and measure the performance with representative I/O-intensive benchmarks. The experimental results show that our scheme effectively improves the I/O performance compared with the ext4 filesystem and prolongs the lifetime of the hybrid buffer cache compared with the Union of Buffer cache and Journaling (UBJ) scheme. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 18:00 | 8.5.3 | FAST LOGIC SYNTHESIS FOR RRAM-BASED IN-MEMORY COMPUTING USING MAJORITY-INVERTER GRAPHS Speaker: Saeideh Shirinzadeh, University of Bremen, DE Authors: Saeideh Shirinzadeh1, Mathias Soeken1, Pierre-Emmanuel Gaillardon2 and Rolf Drechsler3 1University of Bremen, DE; 2University of Utah, US; 3University of Bremen and DFKI, DE Abstract Resistive Random Access Memories (RRAMs) have gained high attention for a variety of promising applications especially the design of non-volatile in-memory computing devices. In this paper, we present an approach for the synthesis of RRAM-based logic circuits using the recently proposed Majority-Inverter Graphs (MIGs). We propose a bi-objective algorithm to optimize MIGs with respect to the number of required RRAMs and computational steps in both MAJ-based and IMP-based realizations. Since the number of computational steps is recognized as the main drawback of the RRAM-based logic, we also present an effective algorithm to reduce the number of required steps. Experimental results show that the proposed algorithms achieve higher efficiency compared to the general purpose MIG optimization algorithms, either in finding a good trade-off between both cost metrics or reducing the number of steps. In comparison with the RRAM-based circuits implemented by the state-of-the-art approaches using other well-known data structures the number of required computational steps obtained by our proposed MIG-oriented synthesis approach for large benchmark circuits is reduced up to factor of 26. This strong gain comes from the use of MIGs that provide an efficient and intrinsic representation for RRAM-based computing---particularly in MAJ-based realizations---and the use of techniques proposed for optimization. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 18:30 | IP4-2, 32 | CAPTOPRIL: REDUCING THE PRESSURE OF BIT FLIPS ON HOT LOCATIONS IN NON-VOLATILE MAIN MEMORIES Speaker: Majid Jalili, Sharif University of Technology, IR Authors: Majid Jalili and Hamid Sarbazi-Azad, Sharif University of Technology, IR Abstract High static power consumption and insufficient scalability of the commonly used DRAM main memory technology appear to be tough challenges in upcoming years. Hence, adopting new technologies, i.e. non-volatile memories (NVMs), is a proper choice. NVMs tolerate a low number of write operations while having good scalability and low static power consumption. Due to the non-destructive nature of a read operation and the long latency of a write operation in NVMs, designers use read-before-write (RBW) mechanism to mask the unchanged bits during write operation in order to reduce bit flips. Based on this observation that some specific locations of blocks are responsible for the majority of bit flips, we extend the RBW to further reduce the number of bit flips per write in the memory system. The results taken from full-system simulations reveal that our proposal, called Captopril, can reduce the number of bit flips by 21% and 9%, on average, compared to the baseline and state-of-the-art designs, respectively Download Paper (PDF; Only available from the DATE venue WiFi) |
| 18:30 | End of session | |