Date: Wednesday 16 March 2016
Time: 11:00 - 12:30
Location / Room: Konferenz 3
Chair:
Robert Wille, JKU, AT
Co-Chair:
Ian O'Connor, Ecole Centrale de Lyon, FR
This session focuses on design methods for biochips. The first paper presents a methodology for synthesizing fault-tolerant biochips. The second paper proposes a synthesis method considering sieve valves, a key component in flow-based microfluidic biochips. Finally the third paper proposes a design automation framework for quantitative gene expression on cyberphysical digital microfluidic biochips.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 11:00 | 6.5.1 | ARCHITECTURE SYNTHESIS FOR COST-CONSTRAINED FAULT-TOLERANT FLOW-BASED BIOCHIPS Speaker: Seetal Potluri, Technical University of Denmark, IN Authors: Morten Chabert Eskesen, Paul Pop and Seetal Potluri, Technical University of Denmark, DK Abstract In this paper, we are interested in the synthesis of fault-tolerant architectures for flow-based microfluidic biochips, which use microvalves and channels to run biochemical applications. The growth rate of device integration in flow-based microfluidic biochips is scaling faster than Moore's law. This increase in fabrication complexity has led to an increase in defect rates during the manufacturing, thereby motivating the need to improve the yield, by designing these biochips such that they are fault tolerant. We propose an approach based on a Greedy Randomized Adaptive Search Procedure (GRASP) for the synthesis of fault-tolerant biochip architectures. Our approach optimizes the introduction of redundancy within a given unit cost budget, such that, the biochemical application can successfully complete its execution within its deadline, even in the presence of faults, and the yield is maximized. The proposed algorithm has been evaluated using several benchmarks and compared to the results of a Simulated Annealing metaheuristic. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 11:30 | 6.5.2 | SIEVE-VALVE-AWARE SYNTHESIS OF FLOW-BASED MICROFLUIDIC BIOCHIPS CONSIDERING SPECIFIC BIOLOGICAL EXECUTION LIMITATIONS Speaker: Mengchu Li, Technische Universität München (TUM), DE Authors: Mengchu Li1, Tsun-Ming Tseng1, Bing Li1, Tsung-Yi Ho2 and Ulf Schlichtmann1 1Technische Universität München (TUM), DE; 2National Tsing Hua University, TW Abstract Microfluidic biochips are being used to perform ever more complex and error-prone bioassays. This results in increasing demand for design automation for such biochips, as these sophisticated designs are beyond the scope of manual design. So far, much research in the field of design automation has been devoted to satisfy this demand from biology, but the gap between design automation and biology is still huge. To narrow this gap, we propose a synthesis method in which sieve valves, which are key components in flow-based microfluidic biochips, are considered for the first time. In addition, we integrate three more constraints into our synthesis that are commonly seen in bioassays but have so far been neglected by design automation: immediate execution, mutual exclusion, and parallel execution. Experiments show that compared with traditional synthesis, this new method shows significant improvements, and the gap between design automation and biology is getting bridged. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 12:00 | 6.5.3 | INTEGRATED AND REAL-TIME QUANTITATIVE ANALYSIS USING CYBERPHYSICAL DIGITAL-MICROFLUIDIC BIOCHIPS Speaker: Mohamed Ibrahim, Duke University, US Authors: Mohamed Ibrahim, Krishnendu Chakrabarty and Kristin Scott, Duke University, US Abstract Considerable effort has recently been directed towards the implementation of molecular bioassays on digital-microfluidic biochips. However, today's solutions suffer from the drawback that multiple sample pathways are not supported and on-chip reconfigurable devices are not efficiently exploited. To overcome this problem, we present a spatial-reconfiguration technique that incorporates resource-sharing specifications into the synthesis flow. This technique is combined with cyberphysical integration to develop the first design-automation framework for quantitative gene expression. The proposed framework is based on a real-time resource-allocation algorithm that responds promptly to decisions about the protocol flow received from a firmware layer. Simulation results show that our adaptive framework efficiently utilizes on-chip resources to reduce time-to-result without sacrificing the chip's lifetime. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 12:30 | End of session Lunch Break in Großer Saal + Saal 1 Keynote Lecture in "Saal 2" 14:00 - 14:30 |