Date: Tuesday 15 March 2016
Time: 11:30 - 13:00
Location / Room: Konferenz 5
Chair:
Vikas Chandra, ARM Research, US
Co-Chair:
Said Hamdioui, TU Delft, NL
Process variation continues to be an important challenge across new technologies. This session explores methods for systematically designing test chips, building photonic interconnects and constructing spatial models.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 11:30 | 2.7.1 | ACHIEVING 100% CELL-AWARE COVERAGE BY DESIGN Speaker: Zeye Liu, Carnegie Mellon University, US Authors: Zeye Liu, Benjamin Niewenhuis, Soumya Mittal and Ronald Blanton, Carnegie Mellon University, US Abstract A comprehensive investigation of new integrated circuit design and fabrication technologies is crucial for yielding reliable parts. Prior work proposed a novel logic characterization vehicle called the Carnegie Mellon Logic Characterization Vehicle (CM-LCV), and an implementation flow that ensures a test chip to be product-like with near optimal testability and diagnosability. This work describes an enhanced implementation methodology for CM-LCV that not only guarantees 100% intra-cell defect testability for all standard cells but also reflects the user-specified design characteristics. Experiments comparing intra-cell defect testability between a CM-LCV and various benchmark circuits demonstrate the efficacy of this approach. Specifically, the CM-LCV achieves 92.4% overall input pattern fault coverage and 100% cell-aware fault coverage using an optimal, minimal test set. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 12:00 | 2.7.2 | (Best Paper Award Candidate) MODELING FABRICATION NON-UNIFORMITY IN CHIP-SCALE SILICON PHOTONIC INTERCONNECTS Speaker: Mahdi Nikdast, Polytechnique Montréal and McGill University, CA Authors: Mahdi Nikdast1, Gabriela Nicolescu2, Jelena Trajkovic3 and Odile Liboiron-Ladouceur4 1Polytechnique Montréal and McGill University, CA; 2Polytechnique Montréal, CA; 3Concordia University, CA; 4McGill University, CA Abstract Silicon photonic interconnect (SPI) is a promising candidate for the communication infrastructure in multiprocessor systems-on-chip (MPSoCs). When employing SPIs with wavelength-division multiplexing (WDM), it is required to precisely match different devices, such as photonic switches, filters, etc, in terms of their central wavelengths. Nevertheless, SPIs are vulnerable to fabrication non-uniformity (a.k.a. process variations), which influences the reliability and performance of such systems. Understanding process variations helps develop system design strategies to compensate for the variations, as well as estimate the implementation cost for such compensations. For the first time, this paper presents a computationally efficient and accurate bottom-up method to systematically study different process variations in passive SPIs. Analytical models to study the impact of silicon thickness and waveguide width variations on strip waveguides and microresonator (MR)-based add-drop filters are developed. Numerical simulations are used to evaluate our proposed method. Furthermore, we designed, fabricated, and tested several identical MRs to demonstrate process variations. The proposed method is applied to a case study of a passive WDM-based photonic switch, which is the building block in passive SPIs, to evaluate its optical signal-to-noise ratio (OSNR) under different variations. The efficiency of our proposed method enables its application to large-scale SPIs in MPSoCs, where employing numerical simulations is not feasible. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 12:30 | 2.7.3 | EFFICIENT SPATIAL VARIATION MODELING VIA ROBUST DICTIONARY LEARNING Speaker: Changhai Liao, Fudan University, CN Authors: Changhai Liao1, Jun Tao1, Xuan Zeng1, Yangfeng Su1, Dian Zhou2 and Xin Li3 1Fudan University, CN; 2Fudan University & The University of Texas at Dallas, US; 3Carnegie Mellon University, US Abstract In this paper, we propose a novel spatial variation modeling method based on robust dictionary learning for nanoscale integrated circuits. This method takes advantage of the historical data to efficiently improve the accuracy of wafer-level spatial variation modeling with extremely low measurement cost. Robust regression is adopted by our implementation to reduce the bias posed by outliers. An iterative coordinate descent method is further introduced to solve the dictionary learning problem with consideration of missing data. Our numerical experiments based on industrial measurement data demonstrate that the proposed method achieves up to 70% error reduction over the conventional VP approach without increasing the measurement cost. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 13:00 | IP1-9, 239 | FAULT TOLERANT NON-VOLATILE SPINTRONIC FLIP-FLOP Speaker: Rajendra Bishnoi, Karlsruhe Institute of Technology (KIT), DE Authors: Rajendra Bishnoi, Fabian Oboril and Mehdi Tahoori, Karlsruhe Institute of Technology (KIT), DE Abstract With technology down scaling, static power has become one of the biggest challenges in a System-On-Chip. Normally-off computing using non-volatile sequential elements is a promising solution to address this challenge. Recently, many non-volatile shadow flip-flop architectures were introduced, in which Magnetic Tunnel Junction (MTJ) cells are employed as backup storing elements. Due to the emerging fabrication processes of magnetic layers, MTJs are more susceptible to manufacturing defects than their CMOS counterparts. Moreover, unlike memory arrays that can effectively be repaired with well-established memory repair and coding schemes, flip-flops scattered in the layout are more difficult to repair. So, without effective defect and fault tolerance for non-volatile flip-flops, the manufacturing yield will be severely affected. Therefore, we propose a Fault Tolerant Non-Volatile Latch (FTNV-L) design, in which we arrange several MTJ cells in such a way that it is resilient to various MTJ faults. Simulation results show that our proposed FTNV-L can effectively tolerate all single MTJ faults with considerably lower overhead than traditional approaches. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 13:01 | IP1-10, 291 | TOWARDS AUTOMATIC DIAGNOSIS OF MINORITY CARRIERS PROPAGATION PROBLEMS IN HV/HT AUTOMOTIVE SMART POWER ICS Speaker: Yasser Moursy, Sorbonne Universités, UPMC, FR Authors: Yasser Moursy1, Hao Zou1, Ramy Iskander1, Pierre Tisserand2, Dieu-My Ton2, Giuseppe Pasetti3, Ehrenfried Seebacher4, Alexander Steinmair4, Thomas Gneiting5 and Heidrun Alius5 1Sorbonne Universités, UPMC, FR; 2Valeo, Creteil, FR; 3AMS, Navacchio, IT; 4AMS AG, Unterpremstaetten, AT; 5AdMOS, Frickenhausen, DE Abstract In this paper, a proposed methodology to identify the substrate coupling effects in smart power integrated circuits is presented. This methodology is based on a tool called AUTOMICS to extract substrate parasitic network. This network comprises diodes and resistors that are able to maintain the continuity of minority carrier concentration. The contribution of minority carriers in the substrate noise is significant in high-voltage and high temperature applications. The proposed methodology along with conventional latch-up problem identification for a test case automotive chip AUTOCHIP1 are presented. The time of the proposed methodology is significantly shorter than the conventional one. The proposed methodology could significantly shorten the time-to-market and ameliorate the robustness of the design. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 13:00 | End of session Lunch Break in Großer Saal + Saal 1 |