Date: Wednesday 11 March 2015
Time: 17:00 - 18:30
Location / Room: Meije
Organisers:
Weisheng Zhao, University Paris‐Sud/CNRS, FR
Lionel Torres, LIRMM, CNRS/University of Montpellier, FR
Chair:
Lionel Torres, LIRMM, CNRS/University of Montpellier, FR
Co-Chair:
Weisheng Zhao, University Paris‐Sud/CNRS, FR
Thanks to its non-volatility, fast data access, low power and infinite endurance, Spintronics (Nobel Prize 2007) is considered as one of the major technologies beyond CMOS to overcome the power and speed bottlenecks of advance computing systems. This topic is under intense study from device to system levels by both academics and industries. This session brings together the worldwide leading experts to share their recent results and discuss future challenges.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 17:00 | 8.5.1 | SPINTRONIC DEVICES AS KEY-ELEMENTS FOR ENERGY-EFFICIENT NEUROINSPIRED ARCHITECTURES Speakers: Nicolas Locatelli1, Adrien F. Vincent2, Alice Mizrahi2, Joseph S. Friedman2, Damir Vodenicarevic2, Joo-Von Kim2, Jacques-Olivier Klein2, Weisheng Zhao3, Julie Grollier4 and Damien Querlioz2 1nstitut d’Electronique Fondamentale, Univ. Paris-Sud, CNRS, FR; 2Institut d’Electronique Fondamentale, Univ. Paris-Sud, CNRS, FR; 3Spintronics Interdisciplinary Center, Beihang University, Beijing, CN; 4Unite Mixte de Physique CNRS/Thales and Universite Paris-Sud, FR Abstract Processing the data deluge using current CMOS architectures requires a remendous amount of energy, as the latter has proved to lack efficiency in tasks such as data mining, recognition and synthesis. Alternative models of computation such as neuroinspiration can be more efficient for this kind of tasks, but do not map ideally to traditional CMOS. Spintronics, in contrast, can offer features such as embedded nonvolatile memory, stochastic and memristive behavior, which, when associated with CMOS, can be key enablers of neuroinspired computing. In this paper, we explore different works that go in this direction. First, we illustrate how recent developments of embedded nonvolatile memory based on magnetic tunnel junctions (MTJs) can ideally provide the large amount of nonvolatile memory required in neuro-inspired designs, while avoiding Von Neumann bottleneck. Second, we show that recently developed spintronics memristors can implement artificial synapses for neuromorphic systems. With a more breakthrough design, we show how probabilistic writing of a single MTJ bit can efficiently replace multi-level weighting in some classes of neuroinspired architectures. Finally, we show that a special class of MTJs can exhibit the phenomenon of stochastic resonance, a strategy used in biological systems to detect weak signals. These results suggest that the impact of spintronics may go far beyond the traditional standalone and embedded memory markets. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 17:20 | 8.5.2 | GIANT SPIN HALL EFFECT (GSHE) LOGIC DESIGN FOR LOW POWER APPLICATION Speakers: Yaojun Zhang1, Bonan Yan1, Wenqing Wu2, Hai Li1 and Yiran Chen1 1University of Pittsburgh, US; 2Qualcomm Incorporated, US Abstract Conventional CMOS transistors will reach its power wall, a huge leakage power consumption limits the performance growth when technology scales down, especially beyond 45nm technology nodes. Spin based devices are one of the alternative computing technologies that aims to replace the current MOS based circuits by taking the advantage of their attractive characteristics, including non-volatility, high integration density and small cell area. The development of technologies such as spin transfer torque random access memory (STT-RAM) and spin torque majority gate logic has become a story of great success. However, most of these technologies faces problems like, small operation margin, poor fan-out ability, etc. As the latest spin technology, Giant Spin Hall Effect (GSHE) Magnetic Tunneling Junction (MTJ) demonstrates a much better operation speed, switching probability and resistance margin. By leveraging the benefit of greater power efficiency and area density, GSHE MTJ elements become a suitable candidate for spintronic logic gates. Compare with traditional MOS transistors based logic gates, GSHE MTJ based logic can operate as a non-volatile memory and requires a much smaller number of elements to perform same logical operations (i.e., 'AND', 'OR', 'NAND' or 'NOR' gate.). And compare with other spin based logics, GSHE MTJ based logic also provides an better performance, excellent CMOS process compatibility and great fan-out ability. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 17:40 | 8.5.3 | SPINTRONICS-BASED NONVOLATILE LOGIC-IN-MEMORY ARCHITECTURE TOWARDS AN ULTRA-LOW-POWER AND HIGHLY RELIABLE VLSI COMPUTING PARADIGM Speakers: Takahiro Hanyu1, Daisuke Suzuki1, Naoya Onizawa1, Shoun Matsunaga2, Masanori Natsui1 and Akira Mochizuki1 1Tohoku University, JP; 2AC Technologies Co., Ltd., JP Abstract Novel logic-LSI architecture, called "spintronics-based nonvolatile logic-in-memory (NV-LIM) architecture," where nonvolatile spintronic storage elements are distributed over a logic-circuit plane, is proposed as a promising candidate to overcome performance wall and power wall due to the present CMOS-only-based logic-LSIs. Some concrete design examples based on the NV-LIM architecture are demonstrated and their usefulness is discussed in comparison with the corresponding CMOS-only-based realization. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 18:00 | 8.5.4 | POTENTIAL APPLICATIONS BASED ON NVM EMERGING TECHNOLOGIES Speakers: Sophiane Senni1, Raphael Martins Brum1, Lionel Torres2, Gilles Sassatelli1, Abdoulaye Gamatie1 and Bruno Mussard3 1LIRMM, FR; 2LIRMM, CNRS/University of Montpellier, FR; 3Crocus technology, FR Abstract Energy efficiency is a critical figure of merit for battery-powered applications. Today's embedded systems suffer from significant increase of power consumption essentially due to a high leakage current in advanced technology node. A significant portion of the total power consumption is spent into memory systems because of an increasing trend of embedded volatile memory area among the building components in System-on-Chips (SoCs). That is why new Non-Volatile Memory (NVM) technologies are considered as a potential solution to solve the energy efficiency issue. Among these NVM technologies, Magnetic RAM (MRAM) is a promising candidate to replace current memories since it combines non-volatility, high scalability, high density, low latency and low leakage. This paper explores use of MRAM into a memory hierarchy (from cache memory to register) of a processor-based system analyzing both performance and energy consumption. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 18:15 | 8.5.5 | FROM DEVICE TO SYSTEM: CROSS-LAYER DESIGN EXPLORATION OF RACETRACK MEMORY Speakers: Guangyu Sun1, Chao Zhang1, Hehe Li2, Yue Zhang3, Weiqi Zhang1, Yizi Gu2, Yinan Sun2, Jacques-Olivier Klein3, Dafine Ravelosona3, Yongpan Liu2, Weisheng Zhao4 and Huazhong Yang2 1Peking University, CN; 2Tsinghua University, CN; 3Univ. Paris-Sud, FR; 4Beihang University, CN Abstract Recently, Racetrack Memory (RM) has attracted more and more attention of memory researchers because it has advantages of ultra-high storage density, fast access speed, and non-volatility. Prior research has demonstrated that RM has potential to replace SRAM for large capacity on-chip memory design. At the same time, it also addressed that the design space exploration of RM could be more complicated compared to traditional on-chip memory technologies for several reasons. First, a single RM cell introduces more device level design parameters. Second, considering these device-level design factors, the layout exploration of a RM array demonstrates trade-off among area, performance, and power consumption of RM circuit level design. Third, in the architecture level, the unique ``shift'' operation results in an extra dimension for design exploration. In this paper, we will review all these design issues in different layers and try to reveal the relationship among them. The experimental results demonstrate that cross-layer design exploration is necessary for racetrack memory. In addition, a system level case study of using RM in a sensor node is presented to demonstrate its advantages over SRAM or STT-RAM. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 18:30 | End of session | |
| 19:30 | DATE Party in Museum of Grenoble (Musée de Grenoble, 5 Place de Lavalette, 38000 Grenoble, France)
As one of the main networking opportunities during the DATE week, the DATE Party states a perfect occasion to meet friends and colleagues in a relaxed atmosphere while enjoying local amenities. It will take place on March 11, 2015, from 19:30 to 23:00 in the renowned "Musée de Grenoble" (Grenoble Museum). This painting museum features a unique collection of ancient, modern and contemporary art including major masterpieces of classical Flemish, Dutch, Italian and Spanish painting and all the great pot-1945 contemporary art-trends, right up to the most recent artwork of the 2000s. During this evening, you can enjoy the famous French Cuisine and outstanding wines. Discover the region of the French Alps through ist cheese and wine specialties. The dinner will be accompanied by jazz songs and instrumental music from Anna Cruz and her vocal band. Another highlight will be the show waders "THE INSEPARABLES", sweet and ephemeral characters walking through the premises, releasing dreams and laughter. Furthermore, at the very beginning of the evening, from 20h00 to 21h30, you will have the opportunity to visit parts of the permanent collection of the museum (ninetieth and twenties century). Please kindly note that it is not a seated dinner. All delegates, exhibitors and their guests are invited to attend the party. Please be aware that entrance is only possible with a valid party ticket. Each full conference registration includes a ticket for the DATE Party (which needs to be booked during the online registration process though). Additional tickets can be purchased on-site at the registration desk (subject to availability of tickets). Price for extra ticket: 60 € per person. How to get there: The tram B has a stop called "Notre Dame Musee". That stop is next to the Museum. Attendees would take the tram A from Alpexpo and change for Tram B in one of the stations between "Gares" and "Maison du Tourisme" to get to the museum. The trip takes about 30 minutes. |
