Date: Tuesday 10 March 2015
Time: 17:00 - 18:30
Location / Room: Stendhal
Chair:
Luciano Lavagno, Politechnico di Torino, IT
Co-Chair:
Aviral Shrivastava, Arrizona State University, US
This session tackles various issues in realistic, complex task scheduling/assignment methods in 2D and 3D multi/many-core systems. The first talk introduces an intra/inter-cores switching method in multi-core scheduling problem for efficient power saving under throughput constraint. The second talk studies thermal-pattern-aware task assignment for 3D multi-core processors, where hotspot is a critical issue, for improving reliability and lifetime. The third talk effectively combines logic solver and background theory solver to synthesize satisfiability modulo theories (SMT)-based systems.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 17:00 | 4.3.1 | AN ONLINE THERMAL-CONSTRAINED TASK SCHEDULER FOR 3D MULTI-CORE PROCESSORS Speakers: Chien-Hui Liao1, Hung-Pin Wen1 and Krishnendu Chakrabarty2 1National Chiao Tung University, TW; 2Duke University, US Abstract Hotspots occur frequently in 3D multi-core processors (3D-MCPs) and they can adversely impact system reliability and lifetime. Moreover, frequent occurrences of hotspots lead to more dynamic voltage and frequency scaling (DVFS), resulting in degraded throughput. Therefore, a new thermal-constrained task scheduler based on thermal-pattern-aware voltage assignment (TPAVA) is proposed in this paper. By analyzing temperature profiles of different voltage assignments, TPAVA pre-emptively assigns different operating-voltage levels to cores for reducing temperature increase in 3D-MCPs. Moreover, the proposed task scheduler integrates a vertical-grouping voltage scaling (VGVS) strategy that considers thermal correlation in 3D-MCPs. Experimental results show that, compared with two previous methods, the proposed task scheduler can respectively lower hotspot occurrences by 47.13% and 53.91%, and improve throughput by 6.50% and 32.06%. As a result, TPAVA and VGVS are effectively for reducing occurrences of hotspots and optimizing throughput for 3D-MCPs under thermal constraints. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 17:30 | 4.3.2 | A SYMBOLIC SYSTEM SYNTHESIS APPROACH FOR HARD REAL-TIME SYSTEMS BASED ON COORDINATED SMT-SOLVING Speakers: Alexander Biewer1, Benjamin Andres2, Jens Gladigau1, Torsten Schaub2 and Christian Haubelt3 1Robert Bosch GmbH, DE; 2University of Potsdam, DE; 3University of Rostock, DE Abstract We propose an SMT-based system synthesis approach where the logic solver performs static binding and routing while the background theory solver computes global time-triggered schedules. In contrast to previous work, we assign additional time to the logic solver in order to refine the binding and routing such that the background theory solver is more likely to find a feasible schedule within a reasonable amount of time. We show by experiments that this coordination of the two solvers results in a considerable reduction of the overall synthesis time. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 18:00 | 4.3.3 | E-PIPELINE: ELASTIC HARDWARE/SOFTWARE PIPELINES ON A MANY-CORE FABRIC Speakers: Xi Zhang1, Haris Javaid1, Muhammad Shafique2, Jorgen Peddersen1, Joerg Henkel2 and Sri Parameswaran1 1University of New South Wales, AU; 2Karlsruhe Institute of Technology (KIT), DE Abstract On-chip many-core systems are expected to be in common use in the future. A set of homogeneous processors in a many-core system can be used to implement multiple pipelines which execute simultaneously. Pipelines of processors use varying numbers of cores when their workloads vary at run time. In this paper, we show how such a system executing multiple pipelines with varying workloads can be implemented. We further show how the system can switch cores within a pipeline (intra-elasticity) and between pipelines (inter-elasticity). The method is named E-pipeline, and is implemented and evaluated in a commercial tool suite. Compared to reference design methods with clock gating, E-pipeline achieves the same power savings, maintains the throughput to meet throughput constraints and reduces core usage by an average of 37.7%. The adaptation overhead for switching cores is approximately 2 us. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 18:30 | End of session | |