Date: Tuesday 10 March 2015
Time: 11:30 - 13:00
Location / Room: Belle Etoile
Chair:
Patrick Knocke, OFFIS, DE
Co-Chair:
Ruzica Jevtic, Universidad Carlos III, ES
Run-time adaptability is increasingly exploited to improve efficiency of energy-scarce systems. This however inevitably brings serious increases in system complexity to optimally control the adaptability knobs and threatens system reliability. This session groups several approaches to achieve effective run-time reconfiguration at various levels of granularity. Adaptive strategies for multi-core task allocation, NV back-up storage, PV energy harvesting and multi-domain clock gating are presented.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 11:30 | 2.2.1 | CLOCK DOMAIN CROSSING AWARE SEQUENTIAL CLOCK GATING Speakers: Mohit Kumar1, Jianfeng Liu2, Mi-Suk Hong2, Kyungtae Do2, JungYun Choi2, Jaehong Park2, Abhishek Ranjan1, Manish Kumar1 and Nikhil Tripathi1 1Calypto Design Systems, IN; 2S.LSI, Samsung Electronics Co. Ltd., KR Abstract Power has become the overriding concern for most modern electronic applications today. To reduce clock power, which is a significant portion of the dynamic power consumed by a design, sequential clock gating is increasingly getting used over and above combinational clock gating. With the shrinking device sizes and increasingly complex designs, data is frequently transferred from one clock domain to the other. The sequential clock gating optimizations can use signals from across sequential boundaries and thus, can introduce new clock domain crossing (CDC) violations which can cause catastrophic functional issues in the fabricated chip. Hence, it has become very important that sequential clock gating optimizations be CDC aware. In this paper, we present an algorithm to handle CDC violations as part of the objective function for sequential clock gating optimizations. With the proposed algorithm, we have obtained an average of 22% sequential power savings — this is within 3% of the power savings obtained by the CDC unaware sequential clock gating. In comparison, the state-of-the-art two-pass solution is leading to an almost complete loss of power savings. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 12:00 | 2.2.2 | AN ENERGY EFFICIENT BACKUP SCHEME WITH LOW INRUSH CURRENT FOR NONVOLATILE SRAM IN ENERGY HARVESTING SENSOR NODES Speakers: Hehe Li1, Yongpan Liu1, Qinghang Zhao1, Guangyu Sun2, Chao Zhang2, Yizi Gu1, Rong Luo1, Huazhong Yang1, Meng-Fan Chang3 and Xiao Sheng1 1Department of Electronic Engineering, Tsinghua University, CN; 2Center for Energy-Efficient Computing and Applications, EECS, Peking University, CN; 3Department of Electrical Engineering, National Tsing Hua University, TW Abstract In modern energy harvesting sensor nodes, nonvolatile SRAM (nvSRAM) has been widely investigated as a promising on-chip memory architecture because of its zero standby power, resilience to power failures, and fast read/write operations. However, conventional approaches transfer all data from SRAM into NVM during the backup process. Thus, large on-chip energy storage capacitors are normally required. In addition, high peak inrush current is generated instantaneously, which has a negative impact on energy efficiency and circuit reliability. To mitigate these problems, we propose a novel holistic backup flow, which consists of a partial backup process and a run-time pre-writeback scheme for nvSRAM based caches. A statistics based dead-block predictor is employed to achieve a fast and low power partial backup process. We also present an adaptive pre-writeback point allocation strategy to further reduce the backup load. Simulation results show that, with our proposed backup scheme, energy storage capacitance is reduced by 34% and inrush current is reduced by 54% on average compared to the conventional full backup scheme. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 12:30 | 2.2.3 | RACE TO IDLE OR NOT: BALANCING THE MEMORY SLEEP TIME WITH DVS FOR ENERGY MINIMIZATION Speakers: Chenchen Fu1, Minming Li1 and Jason Xue2 1Department of Computer Science, City University of Hong Kong, HK; 2City University of Hong Kong, HK Abstract Reducing energy consumption is a critical problem in most of the computing systems today. In recent years, dynamic voltage scaling (DVS) has been often applied in the multi-core processor systems. The leakage power of the main memory shared by the multiple DVS cores is becoming a larger problem with technology scaling. This paper focuses on minimizing the system-wide energy consumption by applying DVS on each core and turning the memory to sleep when all the cores have common idle time. This work presents systematic analysis for the target problem based on different system models and task models. For tasks with common release time , optimal schemes are presented for the systems both with and without considering the static power of the cores. For the general task model, a heuristic online algorithm is proposed. Furthermore, the scheme is extended to handle the problem when the transition overhead between the active and sleep modes is not negligible. The experimental results show that the heuristic algorithm can reduce the energy consumption of the overall system by 8.73% in average (up to 28.44%) compared to a state-of-the-art multi-core DVS scheduling scheme. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 12:45 | 2.2.4 | EVENT-DRIVEN AND SENSORLESS PHOTOVOLTAIC SYSTEM RECONFIGURATION FOR ELECTRIC VEHICLES Speakers: Xue Lin1, Yanzhi Wang1, Massoud Pedram1, Jaemin Kim2 and Naehyuck Chang3 1University of Southern California, US; 2Seoul National University, KR; 3Korea Advanced Institute of Science and Technology, KR Abstract This work investigates the problem of increasing the electrical energy generation efficiency of photovoltaic (PV) systems on electrical vehicles (EVs). Although PV power alone seems simply not sufficient to power an EV, the onboard PV system is still meaningful in mitigating the power demand of EV charging from the grid and reducing the environmental impact of EVs. The PV cell modules of an onboard PV system are mounted on the rooftop, hood, trunk, and door panels of an EV to fully make use of the vehicle surface areas. However, due to the non-uniform distribution and rapid change of solar irradiance, an onboard PV system suffers from significant efficiency degradation. To address this problem, this work borrows the dynamic PV array reconfiguration architecture in previous work with the accommodation of the rapidly changing solar irradiance in the onboard scenario. Most importantly, this work differs from previous work in that (i) we propose an event-driven PV array reconfiguration framework replacing the periodic reconfiguration framework in previous work to reduce the computation and energy overhead of the PV array reconfiguration; (ii) we provide a sensorless (and also event-driven) PV array reconfiguration framework, which further reduces the cost of a vehicular PV system, by proposing a solar irradiance estimation algorithm for obtaining the instantaneous solar irradiance level on each PV cell module. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 13:00 | IP1-1, 208 | HIGH-RESOLUTION ONLINE POWER MONITORING FOR MODERN MICROPROCESSORS Speakers: Fabian Oboril, Jos Ewert and Mehdi Tahoori, Karlsruhe Institute of Technology, DE Abstract The power consumption of computing systems is nowadays a major design constraint that affects performance and reliability. To co-optimize these aspects, fine-grained adaptation techniques at runtime are of growing importance. However, to use these tools efficiently, fine-grained information about the power consumption of various on-chip components at runtime is required. Therefore, here we propose a novel software-implemented high-resolution (spatial and temporal) power monitoring approach that relies on micro-models to estimate the power consumption of all microarchitectural components inside a processor core. Combined with a self-calibration technique that uses an available on-chip power sensor, our power estimation approach can achieve an accuracy of more than 99 % and provides deep insights about the power dissipation inside a processor core during workload execution. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 13:01 | IP1-2, 1013 | REDUCING ENERGY CONSUMPTION IN MICROCONTROLLER-BASED PLATFORMS WITH LOW DESIGN MARGIN CO-PROCESSORS Speakers: Andres Gomez1, Christian Pinto2, Andrea Bartolini3, Davide Rossi2, Hamed Fatemi4, Jose Pineda de Gyvez4 and Luca Benini5 1Swiss Federal Institute of Technology in Zurich (ETHZ), CH; 2Università di Bologna, IT; 3Università di Bologna, IT / ETH Zürich, CH; 4NXP Semiconductors, NL; 5Università di Bologna / Swiss Federal Institute of Technology in Zurich (ETHZ), IT Abstract Advanced energy minimization techniques (i.e. DVFS, Thermal Management, etc) and their high-level HW/SW requirements are well established in high-throughput multi-core systems. These techniques would have an intolerable overhead in low-cost, performance-constrained microcontroller units (MCU's). These devices can further reduce power by operating at a lower voltage, at the cost of increased sensitivity to PVT variation and increased design margins. In this paper, we propose an runtime environment for next-generation dual-core MCU platforms. These platforms complement a single-core with a low area overhead, reduced design margin shadow-processor. The runtime decreases the overall energy consumption by exploiting design corner heterogeneity between the two cores, rather than increasing the throughput. This allows the platform's power envelope to be dynamically adjusted to application-specific requirements. Our simulations show that, depending on the ratio of core to platform energy, total energy savings can be up to 20%. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 13:00 | End of session Lunch Break, Keynote session from 1320 - 1420 (Room Oisans) sponsored by Mentor Graphics in front of the session room Salle Oisans and in the Exhibition area Coffee Break in Exhibition AreaOn all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area. Lunch BreakOn Tuesday and Wednesday, lunch boxes will be served in front of the session room Salle Oisans and in the exhibition area for fully registered delegates (a voucher will be given upon registration on-site). On Thursday, lunch will be served in Room Les Ecrins (for fully registered conference delegates only). Tuesday, March 10, 2015Coffee Break 10:30 - 11:30 Lunch Break 13:00 - 14:30; Keynote session from 13:20 - 14:20 (Room Oisans) sponsored by Mentor Graphics Coffee Break 16:00 - 17:00 Wednesday, March 11, 2015Coffee Break 10:00 - 11:00 Lunch Break 12:30 - 14:30, Keynote lectures from 12:50 - 14:20 (Room Oisans) Coffee Break 16:00 - 17:00 Thursday, March 12, 2015Coffee Break 10:00 - 11:00 Lunch Break 12:30 - 14:00, Keynote lecture from 13:20 - 13:50 Coffee Break 15:30 - 16:00 |