Agenda
Agenda
| Time | Label | Session |
|---|---|---|
| 08:15 | A.1 | Opening Session |
| 08:30 | A.2 | Simulation and Circuit Design |
| 08:30 | A.2.1 | EDA beyond Electronics: Anecdotal Evidence in Systems Biology, MRI Optimization, and Electric Vehicle Simulation Jacob White, MIT, US |
| 09:00 | A.2.2 | Phase Logic Using Self-Sustaining Nonlinear Oscillators Jaijeet Roychowdhury, University of California, Berkeley, US |
| 09:30 | A.3 | Logic Synthesis and Computer Architecture |
| 09:30 | A.3.1 | Towards the Unification of Synthesis and Verification in Logic and Architectural Design Masahiro Fujita, University of Tokyo, JP |
| 10:00 | A.3.2 | From 2-Level to Architectural Synthesis: a Long Trip for Design Automation Jordi Cortadella, Universitat Politècnica de Catalunya, ES |
| 10:30 | A.3.3 | Decomposition of Boolean Expressions 30 Years After the First Algebraic Factoring Algorithm Victor Kravets, IBM, US |
| 11:00 | A.4 | Physical Design and Timing Analysis |
| 11:00 | A.4.1 | Space (and Physical Design): the Final Frontier for VLSI Igor Markov, University of Michigan, US |
| 11:30 | A.4.2 | Technology-Based Logic Transforms Rajeev Murgai, Synopsys, IN |
| 12:00 | A | Lunch Break Buffet meal |
| 13:00 | A.5 | Formal Verification and Equivalence Checking |
| 13:00 | A.5.1 | Combining Algorithms to Solve Intractable Problems Ken McMillan, Microsoft, US |
| 13:30 | A.5.2 | Integrating Induction and Deduction for Verification and Synthesis Sanjit Seshia, University of California, Berkeley, US |
| 14:00 | A.6 | New Frontiers of EDA |
| 14:00 | A.6.1 | New Frontiers of Logic Design Tools Giovanni De Micheli, Ecole Polyt. de Lausanne, CH |
| 14:30 | A.6.2 | Bio-Design Automation: Designing Genetic Circuits with EDA Principles Douglas Densmore, Boston University, US |
| 15:00 | A.7 | Formal Models |
| 15:00 | A.7.1 | Error Localization using Maximal Satisfiability Rupak Majumdar, University of California, Los Angeles, US |
| 15:30 | A.7.2 | The Unknown Component Problem Alexandre Petrenko, CRIM, CA |
| 16:00 | A.8 | System Design |
| 16:00 | A.8.1 | From Latency-Insensitive to Communication-Based System- Level Design Luca Carloni, Columbia University, US |
| 16:30 | A.8.2 | EDA: the Last 40 Years and the next 20 Years Alberto Sangiovanni-Vincentelli, University of California, Berkeley, US |
| 17:00 | A.9 | Conclusions Moderators: |
Robert Brayton
Robert Brayton received the BSEE degree from Iowa State University in 1956 and the Ph.D. degree in mathematics from MIT in 1961. He was a member of the Mathematical Sciences Department of the IBM T. J. Watson Research Center until he joined the EECS Department at Berkeley in 1987. He held the Edgar L. and Harold H. Buttner Endowed Chair and retired as the Cadence Distinguished Professor of Electrical Engineering at Berkeley.
He is a member of the US National Academy of Engineering, an IEEE Fellow, and has received the following awards: IEEE Guilleman-Cauer (1971), ISCAS Darlington (1987), IEEE CAS Technical Achievement (1991), IEEE Emanuel R. Piore (2006), ACM Kanallakis (2006), European DAA Lifetime Achievement (2006), EDAC/CEDA Phil Kaufman (2007), D.O. Pederson best paper in Trans. CAD (2008), ACM/IEEE A. Richard Newton Technical Impact in EDA (2009), Iowa State University Distinguished Alumnus (2010), SRC Technical Excellence (2011) and ACM/SIGDA Pioneering Achievement (2011).
He has co-authored over 460 technical papers, and 11 books in the areas of the analysis of nonlinear networks, simulation and optimization of electrical circuits, logic synthesis, and formal design verification.