W2 Quo Vadis, Virtual Platforms? Challenges and Solutions for Today and Tomorrow

Workshop Format and Structure

The workshop presentations will be by invitation, an open call will be issued for poster session presentations. Poster submissions for each topic area will be reviewed by the workshop organizers and the speakers respectively.

Topic Areas

The workshop will have three main sessions:

System Synthesis – From System-Level Models to (Virtual) Platforms
Virtual Platforms Techniques – State of the Art and Beyond
Implementing Virtual Platforms on Multi-Application Multi-Core Platforms

After each workshop session will be a combined 30-60 min coffee and poster break.

Program

0845	Welcome and Introduction Rainer Leupers – RWTH Aachen University, DE
	SESSION 1: System Synthesis – From System-Level Models to (Virtual) Platforms On today’s Virtual Platforms, the communication is expressed at the transaction-level, usually on top of memory-mapped interconnect models. The mapping and refinement of system-level application models to such platforms is still a challenging task. Exploiting the properties of stricter models of computation (MoC) during this mapping requires knowledge of certain platform artifacts, which may or may not be fixed beforehand.
0900	Recoding Embedded Applications into Flexible System-Level Models Rainer Dömer – University of California, Irvine, US
0930	Actor-Based Virtual Prototype Generation Jürgen Teich – University of Erlangen-Nuremberg, DE
1000	MPSoC Platforms for mobile devices: HW and SW development based on the Nucleus methodology Torsten Kempf – RWTH Aachen University, DE
1030	Poster Session & coffee break (list of posters see below)
	SESSION 2: Virtual Platform Techniques – State of the Art and Beyond With SystemC TLM-2.0, an industrial standard for modeling interoperable Virtual Platforms has been defined. Still, for the platform integration as well as for the analysis of functional and non-functional properties (like power, temperature, etc) different, mainly unconnected approaches exist. In this session, the industrial state-of-the-art for rich Virtual Platform models as well as recent research results and standardization activities are presented.
1100	Scalable Transaction Level Modeling Methodology for Function, Communication, Timing and Power Yossi Veller – Mentor Graphics, IL
1130	Task Modeling and HW/SW partitioning for System Performance Optimization Tim Kogel – Synopsys, DE
1200	LUNCH BREAK
1300	HW/SW Verification from an Open SystemC virtual prototype through simulation, emulation, and FPGA prototyping Leonard Drucker – Cadence, US
1330	High-Level Synthesis, TLM Power State Machines, and advanced tracing for Virtual Platforms Philipp A. Hartmann – OFFIS – Institute for Information Technology, DE
	SESSION 3: Implementing Virtual Platforms on Multi Application Multi-Core Platforms Mapping multiple concurrent applications to multi-core platforms under (hard) real-time constraints is a very challenging task. Multi-core WCET analysis strongly depends on platform details. To achieve composability and segregation of heterogeneous applications running on a single platform, even further (performance, power, etc.) virtualization may be needed. Dedicated platforms providing hardware support for analyzability may be the answer.
1400	Computation Architecture and Platform for Smart Grid Applications Moritz Neukirchner – TU Braunschweig, DE
1430	Poster Session & coffee break (list of posters see below)
1500	CoMPSoC: A Composable and Predictable Execution Platform Kees Goossens – Eindhoven University of Technology (TU/e), NL
1530	Cross-Domain Reference Architecture for Embedded Systems Roman Obermaisser – University of Siegen, DE
1600	Closing Remarks Christian Haubelt – University of Rostock, DE
1615	CLOSE

POSTERS:

Virtual Platform Generation Using TECS Software Component and SCE
Takuya Azumi - Ritsumeikan University, JP
Yuko Hara-Azumi - Ritsumeikan University, JP
Rainer Dömer - University of California, Irvine, US

Architecture Exploration of Multicore Systems-on-Chip using a TLM-based Framework
Mona Safar - Ain Shams University, ET
Magdy El-Moursy - Mentor Graphics Corporation, ET
Mohamed Abdelsalam - Mentor Graphics Corporation, ET
Ashraf Salem - Technology Innovation and Entrepreneurship Center (TIEC), ET

Virtual Platform for Mixed-Time Criticality Applications: The CoMPSoC Architecture and SDF3 Design Flow
Benny Akesson - Eindhoven University of Technology, NL
Sander Stuijk - Eindhoven University of Technology, NL
Anca Molnos - Delft University of Technology, NL
Martjin Koedam - Eindhoven University of Technology, NL
Radu Stefan - Eindhoven University of Technology, NL
Andrew Nelson - Delft University of Technology, NL
Ashkan Beyranvand - Delft University of Technology, NL
Kees Goossens - Eindhoven University of Technology, NL

Source-Level Timing Simulation of Embedded Software Considering Compiler Optimizations
Stefan Stattelmann - FZI Forschungszentrum Informatik, DE
Oliver Bringmann - FZI Forschungszentrum Informatik, DE
Wolfgang Rosenstiel - University of Tuebingen, DE

Efficient Analysis of SystemC Models
Simon Roth, BOSCH GmbH, DE
Wolfgang Rosenstiel - University of Tuebingen, DE

Virtual Platform for Embedded System Power Estimation
Santhosh Kumar Rethinagiri - INRIA Lille Nord Europe, Univ. of Valenciennes, FR
Rabie Benatitallah - UVHC/LAMIH, FR
Jean-Luc Dekeyser - Inria, FR

Domain Specific Virtual Platforms
Francisco Mendoza - FZI Forschungszentrum Informatik, DE
Juergen Becker - Karlsruhe Institute of Technology, DE

Dynamic Resource Management for Virtualized Mixed-Criticality Systems
Stefan Groesbrink - University of Paderborn, DE
Simon Oberthuer - University of Paderborn, DE
Daniel Baldin - University of Paderborn, DE

Quo Vadis, Virtual Platforms? A Posse ad Esse, hic Platforma Vitutis Est!
Graham Hellestrand - Embedded Systems Technology, Inc., US

Scalable Multi-Core Virtualization for Embedded System-on-Chip Architectures
Alexander Biedermann - TU Darmstadt, DE
Sorin Huss - TU Darmstadt, DE

Poster Submission Instructions

Authors are invited to submit contributions as up to 2-page long abstracts. On-going works are welcome. All submissions must be written in English, and only PDF files are accepted. All 2-pages abstract must be prepared in accordance with the DATE manuscript style [1]. All submitted 2-page abstracts should clearly identify the relevant session (System Synthesis, Virtual Platforms Techniques, or Implementing Virtual Platforms on Multi-Application Multi-Core Platforms) and will undergo the same review process (at least 2 reviews per contribution).

Link to Call for Posters (pdf) [2]

Link to submission system: https://www.easychair.org/conferences/?conf=qvvp12 [3]

Important dates

Deadline for 2-page abstract submission (extended): November 04, 2011 November 30, 2011
Notification of acceptance (extended): December 02, 2011 December 23, 2011
Final 2-page abstract and one page poster submission: February 03, 2012

Proceedings

A workshop digest based upon the 2-page abstract and one-page poster will be distributed to all participants of the workshop. In addition to the workshop digest, the organizers plan to invite selected speaker and poster presenters to submit original work to a Springer Book on “Virtual Platforms for MPSoC Design: Principles & Practice”.

Note that the posters presented at the DATE workshops are NOT disseminated through the official DATE proceedings or through any other formal channels, such as, for example, the IEEExplore or the ACM Digital Library.

Program Committee

Rainer Dömer (USA)
Leonard Drucker (USA)
Rolf Ernst (DE)
Kees Goossens (NL)
Kim Grüttner (DE)
Philipp A. Hartmann (DE)
Christian Haubelt (DE)
Tim Kogel (DE)
Rainer Leupers (DE)
Adam Morawiec (FR)
Moritz Neukirchner (DE)
Roman Obermaisser (DE)
Achim Rettberg (DE)
Jürgen Teich (DE)
Yossi Veller (IL)