SPEAKERS' BIOGRAPHIES
Patrick Girard received a M.S. degree in Electrical Engineering and a Ph.D. degree in Microelectronics from the University of Montpellier, France, in 1988 and 1992 respectively. He is currently Research Director at CNRS (French National Center for Scientific Research), and Head of the Microelectronics Department of the LIRMM (Laboratory of Informatics, Robotics and Microelectronics of Montpellier - France). His research interests include all aspects of digital testing and memory testing, with emphasis on critical constraints such as timing and power. From 2006 to 2010, Patrick Girard was Vice-Chair of the European Test Technology Technical Council (ETTTC) of the IEEE Computer Society. He has served on numerous conference committees including ACM/IEEE Design Automation Conference (DAC), ACM/IEEE Design Automation and Test in Europe (DATE), IEEE International Test Conference (ITC), IEEE International Conference on Computer Design (ICCD), IEEE VLSI Test Symposium (VTS), IEEE European Test Symposium (ETS), IEEE Asian Test Symposium (ATS), and ACM/IEEE International Symposium on Low Power Electronic Design (ISLPED). Patrick Girard is the founder and Editor-in-Chief of the ASP Journal of Low Power Electronics (JOLPE). He is an Associate Editor of the IEEE Transactions on VLSI Systems and the Journal of Electronic Testing – Theory and Applications (JETTA - Springer). From 2005 to 2009, he was an Associate Editor of the IEEE Transactions on Computers. He is a co-editor of the book “Power-Aware Testing and Test Strategies for Low Power Devices”, Springer, 2009, and a co-author of the book “Advanced Test Methods for SRAMs – Effective Solutions for Dynamic Fault Detection in Nanoscale Technologies”, Springer, 2009. Patrick Girard has been involved in several European research projects (ESPRIT III ATSEC, EUREKA MEDEA, MEDEA+ ASSOCIATE, IST MARLOW, MEDEA+ NanoTEST, CATRENE TOETS) and has managed industrial research contracts with major companies like Infineon Technologies, Atmel, STMicroelectronics, etc. He has supervised 22 PhD dissertations and has published 6 books or book chapters, 34 journal papers, and more than 110 conference and symposium papers on these fields. He received two Best Paper Awards (ETS 2004 and DDECS 2005). Patrick Girard is a Senior Member of IEEE.
Nicola Nicolici is an Associate Professor in the Department of Electrical and Computer Engineering at McMaster University, Canada. He received the Dipl. Ing. degree in Computer Engineering from the Politehnica” University of Timisoara, Romania (1997), and a Ph.D. in Electronics and Computer Science from the University of Southampton, U.K. (2000). His research interests are in the area of computer aided design and test. He has authored over fifty research papers and one book in this area and received the IEEE TTTC Beausang Award for the Best Student Paper at the International Test Conference (ITC 2000) and the Best Paper Award at the IEEE/ACM Design Automation and Test in Europe Conference (DATE 2004). Currently he is on the technical program committee for the DATE, IEEE/ACM Design Automation Conference (DAC), IEEE European Test Symposium (ETS), IEEE Defect and Fault Tolerance Symposium (DFT), IEEE Asian Test Symposium (ATS), IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS), IEEE Workshop on Silicon Debug and Diagnosis (SDD), and he serves as the Program Co-Chair for Diagnostic Services in Network-on-Chips Workshop. He was the guest co-editor for a special issue on Silicon Debug and Diagnosis (to be published by IET Proceedings on Computers and Digital Techniques) and a special issue on Low Power Test (to be published by for the Journal of Electronic Testing – Theory and Applications). He is a member of the ACM SIGDA and the IEEE Computer and Circuits and Systems Societies.
Xiaoqing Wen received a B.E. degree from Tsinghua University, Beijing China, in 1986, a M.E. degree from Hiroshima University, Hiroshima, Japan, in 1990, and a Ph.D degree from Osaka University, Osaka, Japan, in 1993. From 1993 to 1997, he was a Lecturer at Akita University, Akita, Japan. He was a Visiting Researcher at University of Wisconsin, Madison, U.S.A., from October 1995 to March 1996. He joined SynTest Technologies, Inc., U.S.A., in 1998, and served as its CTO until 2003. In January 2004, he joined the Kyushu Institute of Technology, Iizuka, Japan, where he is currently a Professor. He was the Program Committee Co-Chair of the Sixteenth IEEE Asian Test Symposium and the Eighth IEEE Workshop on RTL and High Level Testing. Currently, he is on numerous program committees, including IEEE/ACM Design Automation Conference (DAC), IEEE International Test Conf. (ITC), Design, Automation, and Test in Europe (DATE), IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS), European Test Symposium (ETS), and Asian Test Symposium (ATS). He is the Associate Editor for Journal of Computer Science and Technology) and the Information Processing Society Transactions on System LSI Design Methodology. He co-authored and coedited two books: VLSI Test Principles and Architectures: Design for Testability (San Francisco, CA: Morgan Kaufmann, 2006) and Power-Aware Testing and Test Strategies for Low Power Devices (New York, NY: Springer, 2009). His research interests include design, test, and diagnosis of integrated circuits. He currently holds 23 U.S. Patents and 5 Japan Patents in logic built-in self-test (BIST), test compression, and low-power test generation. He received the 2008 IEICE-ISS Best Paper Award. He is a member of the IEICE, the IPSJ, and the REAJ.