SPEAKERS' BIOGRAPHIES
Prof. David Atienza is Professor and Director of the Embedded Systems Laboratory (ESL) at the Institute of Electrical Engineering within the School of Engineering of EPFL (Switzerland). He received his M.Sc. and Ph.D. degrees in Computer Science and Enginering from Complutense University (Spain) and IMEC (Belgium), in 2001 and 2005, respectively. He is co-author of more than 140 publications in prestigious journals and international conferences. He received the "2009 Best Technical Paper Award" at the 17th IEEE/IFIP VLSI-SoC Conference and nominations for the "2004 DAC Best Paper Award" and "2006 ICCAD Best Paper Award". Also, he is an Associate Editor of IEEE Transactions on CAD (in the area of System-Level Design), IEEE Letters on Embedded Systems and Elsevier Integration: The VLSI Journal, as well as Technical Program Chair of GLSVLSI 2010 and VLSI-SoC 2011, and TPC member of DATE, ASP-DAC, ICCAD, ISVLSI, GLSVLSI, VLSI-SoC, RTAS, SBCCI and PATMOS conferences. He is an elected member of the Executive Committee of the IEEE CEDA since 2008, and GOLD member of the Board of Governors of the IEEE CASS since 2009.
Dr. Tanay Karnik received his Ph.D. in Computer Engineering from the University of Illinois at Urbana-Champaign in 1995. From 1995 to 1999, he worked in the Strategic CAD Lab at Intel. Since March 1999, he has lead the power delivery, soft error rate, and low power circuits research in the Circuits Research, Intel Labs, where he is Principal Engineer and manager of low power circuits research. His research interests are in the areas of variation tolerance, power delivery, soft errors and physical design. He has published over 40 technical papers, has 46 issued and 32 pending patents in these areas. He received an Intel Achievement Award for the pioneering work on integrated power delivery. He has presented several invited talks and tutorials, and has served on 5 PhD students'committees. He was a member of ISSCC, DAC, ICCAD, ICICDT and ISQED program committees and JSSC, TCAD, TVLSI, TCAS review committees. Tanay was Technical Program Chair of ASQED’09 and General Chair of ISQED'08, ISQED’09 and ICICDT'08. Tanay is a Senior Member of IEEE and Fellow of ISQED.
Mr. Patrick Leduc received his M. Sc. degree in physics from the Polytechnics Institute of Grenoble (Ecole Phelma), France, in 1998 and joined the CEA-LETI in 2000. His current position is project leader in 3-D integration for CMOS applications. His fields of expertise are CMOS interconnects technologies and mechanical integrity of back-end structures. During 5 years, he has been working on process development (Chemical Mechanical Planarization) for CMOS interconnects. Since 2006, he is in charge of 3D integration projects. He participated in European projects dedicated to interconnects (NanoCMOS, Pullnano, ELITE). During his carrier, he has been author or co-author of about 30 technical papers, communications or invited presentations in international conferences related to the above fields. He has given five invited talks on 3-D integration in international conferences. He is co-author of Wiley-vch handbook of 3-D IC Integration.
Prof. Sachin S. Sapatnekar holds the Distinguished McKnight University Professorship and the Henle Chair in Electrical and Computer Engineering at the University of Minnesota. He received the Ph.D. degree from the University of Illinois at Urbana-Champaign in 1992, and has published widely in various areas of CAD. He has been actively involved with several major conference and journals, and is General Chair for the 2010 Design Automation Conference and Editor-in-Chief of the IEEE Transactions on CAD. He has received six Best Paper Awards, the NSF Career Award, and the SRC Technical Excellence Award. He is a Fellow of the IEEE.
Dr. Jeonghee Shin is a Research Staff Member at IBM T. J. Watson Research Center. She is currently working on early processor design automation and 3D chip planning. Her research interests are in the area of design automation, productivity, and computer architecture. Jeonghee received her PhD degree in Computer Engineering at the University of Southern California in 2008, focusing on lifetime reliability-aware design and modeling, and interconnection networks.